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october 2003 1/268 . st92196a st92t196 st92e196 8/16-bit mcu for tv applications with up to 96k rom, on-screen-display and 1 or 2 data slicers n register file based 8/16 bit core architecture with run, wfi, and halt modes n -10 to 75 c operating temperature range n 24 mhz operation @5 v 10% n min. instruction cycle time: 165 ns at 24 mhz n 32 - 96 kbytes rom, 1 - 3 kbytes static ram n 256 bytes of register file n 384 bytes of display ram (osdram) n 56-pin shrink dip and tqfp64 packages n 37 fully programmable i/o pins n flexible clock controller for osd, data slicer and core clocks, running from one single low frequency external crystal n enhanced display controller with rows of up to 63 characters per row C 50/60hz and 100/120 hz operation C 525/625 lines operation, 4/3 or 16/9 format C interlaced and progressive scanning C 18x26 or 9x13 character matrix C 384 (18x26) characters, or 1536 (9x13) char- acters definable in rom by user C 512 possible colors, in 4x16-entry palettes C 2 x 16-entry palettes for foreground, and 2 x 16-entry palettes for background C 8 levels of translucency on fast blanking C serial, parallel and extended parallel at- tribute modes C mouse pointers user-definable in rom C 7 character sizes in 18x26 mode, 4 in 9x13 C rounding, fringe, scrolling, flashing, shad- owing, italics, semi-transparent n i 2 c multi-master / slave with 4 channels n serial communications interface (sci)* n serial peripheral interface (spi) n 8-channel a/d converter with 6-bit accuracy n 16-bit watchdog timer with 8-bit prescaler n 14-bit voltage synthesis for tuning reference voltage with 2 outputs for 2 tuners n 16-bit standard timer with 8-bit prescaler n 16-bit multi-function timer* n eight 8-bit programmable pwm outputs n nmi and 6 external interrupts n 1 or 2 data slicers for closed captioning and extended data service data extraction, on 2 independent video sources. support for fcc v- chip and gemstar bitstream decoding n infra-red signal digital pre-processor n 2-channel sync error detection with integrated sync extractor n rich instruction set and 14 addressing modes n versatile development tools, including c- compiler, assembler, linker, source level debugger, emulator and real-time operating systems from third-parties n windows based osd font and screen editor device summary device rom ram slicers sci mft st92196a7 96k 3k 2 1 1 st92196a6 2k 211 st92196a4 64k 2-1 st92196a3 1 - - st92196a2 48k 1k 1-- st92196a1 32k 1 - - tqfp64 psdip56 1 * on some devices
2/ 268 st92196a st92196a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.1 core architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.2 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.3 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.4 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2.1 i/o port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2.2 i/o port reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.3 required external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.4 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5 st92196a register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2 device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.1 core architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2 memory spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.1 register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.2 register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3 system registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3.1 central interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3.2 flag register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 2.3.3 register pointing techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3.4 paged registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.5 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.6 stack pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 2.4 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.5 memory management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.6 address space extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.6.1 addressing 16-kbyte pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.6.2 addressing 64-kbyte segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.7 mmu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.7.1 dpr[3:0]: data page registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.7.2 csr: code segment register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.7.3 isr: interrupt segment register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.7.4 dmasr: dma segment register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.8 mmu usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.8.1 normal program execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.8.2 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.8.3 dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.2 interrupt vectoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.2.1 divide by zero trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.2.2 segment paging during interrupt routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2
3/ 268 st92196a 3.3 interrupt priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.4 priority level arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.4.1 priority level 7 (lowest) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.4.2 maximum depth of nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.4.3 simultaneous interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.4.4 dynamic priority level modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.5 arbitration modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.5.1 concurrent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.5.2 nested mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.6 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.7 top level interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.8 on-chip peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.9 interrupt response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.10 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4 on-chip direct memory access (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.2 dma priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.3 dma transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.4 dma cycle time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.5 swap mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.6 dma registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5 reset and clock control unit (rccu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.2 clock control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.3 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.3.1 halt state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 5.4 reset/stop manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6 timing and clock controller (tcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.1 frequency multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.2 specific port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.3 port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.4 input/output bit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.5 alternate function architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.5.1 pin declared as i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.5.2 pin declared as an alternate function input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.5.3 pin declared as an alternate function output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.6 i/o status after wfi, halt and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 8.1 timer/watchdog (wdt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 8.1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4/ 268 st92196a 8.1.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.1.3 watchdog timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.1.4 wdt interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.1.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.2 standard timer (stim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 8.2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 8.2.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8.2.3 interrupt selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8.2.4 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8.2.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.3 multifunction timer (mft) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.3.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.3.3 input pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 8.3.4 output pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.3.5 interrupt and dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.3.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 8.4 osdram controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 11 8.4.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.4.3 osdram controller reset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.5 on screen display controller (osd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 14 8.5.2 general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.5.4 horizontal and vertical sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 8.5.5 programming the display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 8.5.6 programming the color palettes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 8.5.7 programming the mouse pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 8.5.8 programming the row buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 8.5.9 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 8.6 closed caption data slicer (ds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 8.6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 60 8.6.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 8.6.3 data slicer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.6.4 interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 8.6.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 8.7 video sync error detector (syncerr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 8.7.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 8.7.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 8.8 ir preprocessor (ir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 8.8.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 8.8.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 8.9 four-channel i 2 c bus interface (i2c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 8.9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 70 8.9.2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 8.9.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
5/ 268 st92196a 8.9.4 interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 8.9.5 error cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 8.9.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 8.10 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 8.10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 8.10.2 device-specific options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 8.10.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 8.10.4 interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 8.10.5 working with other protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 8.10.6 i2c-bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 8.10.7 s-bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 8.10.8 im-bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 8.10.9 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 8.11 serial communications interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 8.11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 8.11.2 sci operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 8.11.3 serial frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 8.11.4 clocks and serial transmission rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 8.11.5 sci initialization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 8.11.6 input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 97 8.11.7 output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 8.11.8 interrupts and dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 8.11.9 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 8.12 voltage synthesis tuning converter (vs) . . . . . . . . . . . . . . . . . . . . . . . . . . 209 8.12.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 8.12.2 output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 8.12.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 8.13 pwm generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 8.13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 8.13.2 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 8.14 a/d converter (a/d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 8.14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 8.14.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 8.14.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 8.14.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 9 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 10 package description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3 11 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 st92e196a/b & st92t196a/b . . . . . . . . . . . . . . . . . . . . . . . . 236 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 1.1.1 core architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 1.1.2 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 1.1.3 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 1.1.4 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 40
6/ 268 st92196a 1.2.1 i/o port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 1.2.2 i/o port reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 1.3 required external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 1.4 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 1.5 st92e196a/b & st92t196a/b register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 3 eprom/otp programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 4 package description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 63 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4 12 summary of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
7/ 268 st92196a
8/268 general description 1 general description 1.1 introduction the st92196a family brings the enhanced st9 register-based architecture to a new range of high- performance microcontrollers specifically de- signed for tv applications. their performance de- rives from the use of a flexible 256-register pro- gramming model for ultra-fast context switching and real-time event response. the intelligent on- chip peripherals offload the st9 core from i/o and data management processing tasks allowing criti- cal application tasks to get the maximum use of core resources. the st9 mcu devices support low power consumption and low voltage operation for power-efficient and low-cost embedded sys- tems. 1.1.1 core architecture the nucleus of the st92196a is the enhanced st9 core that includes the central processing unit (cpu), the register file, the interrupt and dma controller. three independent buses are controlled by the core: a 16-bit memory bus, an 8-bit register ad- dressing bus and a 6-bit interrupt/dma bus which connects the interrupt and dma controllers in the on-chip peripherals with the core. this multiple bus architecture makes the st9 fam- ily devices highly efficient for accessing on and off-chip memory and fast exchange of data with the on-chip peripherals. the general-purpose registers can be used as ac- cumulators, index registers, or address pointers. adjacent register pairs make up 16-bit registers for addressing or 16-bit processing. although the st9 has an 8-bit alu, the chip handles 16-bit opera- tions, including arithmetic, loads/stores, and mem- ory/register and memory/memory exchanges. many opcodes specify byte or word operations, the hardware automatically handles 16-bit opera- tions and accesses. for interrupts or subroutine calls, the cpu uses a system stack in conjunction with the stack pointer (sp). a separate user stack has its own sp. the separate stacks, without size limitations, can be in on-chip ram (or in register file) or off-chip mem- ory. 1.1.2 instruction set the st9 instruction set consists of 94 instruction types, including instructions for bit handling, byte (8-bit) and word (16-bit) data, as well as bcd and boolean formats. instructions have been added to facilitate large program and data handling through the mmu, as well as to improve the performance and code density of c function calls. 14 address- ing modes are available, including powerful indi- rect addressing capabilities. the st9's bit-manipulation instructions are set, clear, complement, test and set, load, and various logic instructions (and, or, and xor). math func- tions include add, subtract, increment, decrement, decimal adjust, multiply, and divide. 1.1.3 operating modes to optimize performance versus the power con- sumption of the device, st9 devices now support a range of operating modes that can be dynami- cally selected depending on the performance and functionality requirements of the application at a given moment. run mode. this is the full speed execution mode with cpu and peripherals running at the maximum clock speed delivered by the phase locked loop (pll) of the clock control unit (ccu). slow mode . power consumption can be signifi- cantly reduced by running the cpu and the periph- erals at reduced clock speed using the cpu pres- caler and ccu clock divider. wait for interrupt mode. the wait for interrupt (wfi) instruction suspends program execution un- til an interrupt request is acknowledged. during wfi, the cpu clock is halted while the peripheral and interrupt controller keep running at a frequen- cy programmable via the ccu. in this mode, the power consumption of the device can be reduced by more than 95% (low power wfi). halt mode. when executing the halt instruction, and if the watchdog is not enabled, the cpu and its peripherals stop operating and the status of the machine remains frozen (the clock is also stopped). a reset is necessary to exit from halt mode. 3
9/268 general description introduction (contd) figure 1. st92196a architectural block diagram *on some devices only note : not all peripherals are available on all device versions. please check the device summary on page 1. watchdog timer 256 bytes register file 1 to 3k ram st9+ core 8/16 bits cpu dma/interrupt management memory bus rccu cc data slicer 1 register bus a/d converter ccvideo1 dsout1 sci* 32 to 96k rom ain[7:0] extrg sin0 sout0 all alternate functions ( italic characters ) are mapped on ports 0, 2, 3, 4, and 5 sda[4:0] scl[4:0] mf timer* oscin oscout reset reseti 4 ch. i 2 c bus p0[7:0] p2[7:0] p3[7:0] p4[7:0] p5[6:5,2:0] tina tinb touta toutb int[7:0] nmi fully prog. i/os sdio sck spi osdram controller 384 bytes ram infra-red preprocessor pwm dac cc data slicer 2* sync error detector osd voltage synthesis ir pwm[7:0] syndet0 syndet1 vso1 vso2 ccvideo2 dsout2 hsync vsync r/g/b/fb tslu pixclk frequency multiplier fcpu fosd stim timer
10/268 general description introduction (contd) 1.1.4 on-chip peripherals osd controller the on screen display displays closed caption or extended service format data received from the on-chip data slicers or any text or menu data gen- erated by the application. rows of up to 63 charac- ters can be displayed with two user-definable fonts. colors, character shape and other attributes are software programmable. support is provided for mouse or other pointing devices. parallel i/o ports the st9 is provided with dedicated lines for input/ output. these lines, grouped into 8-bit ports, can be independently programmed to provide parallel input/output or to carry input/output signals to or from the on-chip peripherals and core e.g. sci and multifunction timer. all ports have active pull-ups and pull-down resistors compatible with ttl loads. in addition pull-ups can be turned off for open drain operation and weak pull-ups can be turned on to save chip resistive pull-ups. input buffers can be either ttl or cmos compatible. multifunction timer the multifunction timer has a 16-bit up/down counter supported by two 16-bit compare regis- ters and two 16-bit input capture registers. timing resolution can be programmed using an 8-bit pres- caler. serial communications controller the sci provides an asynchronous serial i/o port using two dma channels. baud rates and data for- mats are programmable. controller applications can further benefit from the self test and address wake-up facility offered by the character search mode. i 2 c bus interface the i 2 c bus is a synchronous serial bus for con- necting multiple devices using a data line and a clock line. multimaster and slave modes are sup- ported. up to four channels are supported. the i 2 c interface supports 7-bit addressing. it operates in multimaster or slave mode and supports speeds of up to 666.67 khz. bus events (bus busy, slave ad- dress recognised) and error conditions are auto- matically flagged in peripheral registers and inter- rupts are optionally generated. analog/digital converter the adc provides up to 8 analog inputs with on- chip sample and hold. conversion can be trig- gered by a signal from the mft.
11/268 general description 1.2 pin description figure 2. 64-pin thin qfp package pin-out n.c. = not connected * not available on some devices. n.c. ain6/p0.6 ain5/p0.5 ain4/p0.4 ain0/p0.3 p0.2 p0.1 p0.0 ccvideo1 v dd2 ccvideo2*/p3.7 syndet0/dsout1/p3.6 sda2/tina*/p3.5 scl2/touta*/int1/p3.4 syndet1/dsout2*/p3.3 n.c. n.c. p0.7/ain7 p2.7/int5/pixclk p2.6/nmi p2.5/sda1/sdio p2.4/int2/scl1/sck p5.6/pwm3 p5.5/pwm2 v pp test0 p5.2/sout0* p5.1/sin0* p.5.0/reseti reset p4.7/pwm7/extrg n.c. n.c. p4.6/pwm6 p4.5/pwm5 p4.4/pwm4 p4.3 p4.2 p4.1/sda4/tinb*/pwm1 p4.0/scl4/toutb*/pwm0 oscin v ss2 oscout p2.3/ain3/vso2/int4 p2.2/ain2/vso1/int3 p2.1/ain1/int6 p2.0/ir/int7 n.c. n.c. int0/p3.2 sda3/p3.1 scl3/tslu/p3.0 fb b g r v dd1 v ss1 fcpu v dda fosd vsync hsync n.c. 1 64 16 32 48 16
12/268 general description pin description (contd) figure 3. 56-pin package pin-out * not available on some devices. table 1. power supply pins table 2. primary function pins 156 29 28 v pp test0 p5.2/sout0* p5.1/sin0* p5.0/reseti reset p4.7/pwm7/extrg p4.6/pwm6 p4.5/pwm5 p4.4/pwm4 p4.3 p4.2 p4.1/sda4/tinb*/pwm1 p4.0/scl4/toutb*/pwm0 oscin v ss2 oscout p2.3/ain3/vso2/int4 p2.2/ain2/vso1/int3 p2.1/ain1/int6 p2.0/ir/int7 hsync vsync fosd v dda fcpu v ss1 v dd1 pwm2/p5.5 pwm3/p5.6 sck/scl1/int2/p2.4 sdio/sda1p2.5 nmi/p2.6 pixclk/int5/p2.7 ain7/p0.7 ain6/p0.6 ain5/p0.5 ain4/p0.4 ain0/p0.3 p0.2 p0.1 p0.0 ccvideo1 v dd2 ccvideo2*/p3.7 dsout1/syndet0/p3.6 tina*/sda2/p3.5 int1/touta*/scl2/p3.4 dsout2/syndet1/p3.3 int0/p3.2 sda3/p3.1 tslu/scl3/p3.0 fb b g r name function sdip56 qfp64 v dd1 v dd2 main power supply voltage (2 pins internally connected) 29 25 16 10 v ss1 v ss2 analog and digital circuit ground (2 pins internally connected) 30 26 41 39 v dda analog circuit supply voltage 32 28 v pp eprom programming voltage. must be connected to v dd in nor- mal operating mode. 56 56 name function sdip56 qfp64 oscin oscillator input 42 40 oscout oscillator output 40 38 reset reset to initialize the st9 51 51 hsync video horizontal sync input (schmitt trigger) 35 31 vsync video vertical sync input (sch- mitt trigger) 34 30 r red video analog dac output 28 24 g green video analog dac output 27 23 b blue video analog dac output 26 22 fb fast blanking analog dac output 25 21 ccvideo1 closed caption composite video input 1 (2v +/- 3 db) 15 9 fcpu cpu frequency multiplier filter output 31 27 fosd osd frequency multiplier filter output 33 29 test0 test input (must be tied to v dd )5555
13/268 general description pin description (contd) 1.2.1 i/o port configuration all ports can be individually configured as input, bi- directional, output, or alternate function. refer to the port bit configuration table in the i/o port chapter. no i/o pins have any physical weak pull-up capa- bility (they will show no pull-up if they are pro- grammed in the "weak pull-up" software mode). input levels can be selected on a bit basis by choosing between ttl or cmos input levels for i/ o port pin except for p2.(5:4,0), p3.(6:3,1:0), p4.(1:0) which are implemented with a schmitt trigger function. all port output configurations can be software se- lected on a bit basis to provide push-pull or open drain driving capabilities. for all ports, when con- figured as open-drain, the voltage on the pin must never exceed the v dd power line value (refer to electrical characteristics section). 1.2.2 i/o port reset state i/os are reset asynchronously as soon as the re- set pin is asserted low. all i/o are forced by the reset in bidirectional, high impedance output due to the lack of physical pull- up except p5.0 (refer to the reset section) which is forced into the "push-pull alternate function" mode until being reconfigured by software. warning when a common pin is declared to be connected to an alternate function input and to an alternate function output, the user must be aware of the fact that the alternate function output signal always in- puts to the alternate function module declared as input. when any given pin is declared to be connected to a digital alternate function input, the user must be aware of the fact that the alternate function input is always connected to the pin. when a given pin is declared to be connected to an analog alternate function input (adc input for example) and if this pin is programmed in the "af-od" mode, the digit- al input path is disconnected from the pin to pre- vent any dc consumption. table 3. i/o port characteristics legend: od = open drain, af = alternate function input output weak pull-up reset state port 0[7:0] ttl/cmos push-pull/od no bidirectional port 2.0 port 2[3:1] port 2[5:4] port 2[7:6] schmitt trigger ttl/cmos schmitt trigger ttl/cmos push-pull/od push-pull/od push-pull/od push-pull/od no no no no bidirectional bidirectional bidirectional bidirectional port 3.0 port 3.1 port 3.2 port 3[6:3] port 3.7 schmitt trigger schmitt trigger ttl/cmos schmitt trigger ttl/cmos push-pull/od push-pull/od push-pull/od push-pull/od push-pull/od no no no no no bidirectional bidirectional bidirectional bidirectional bidirectional port 4.[1:0] port 4.[7:2] schmitt trigger ttl/cmos push-pull/od push-pull/od no no bidirectional bidirectional port 5.0 port 5[6:1] ttl/cmos ttl/cmos push-pull/od push-pull/od no no push-pull af out bidirectional
14/268 general description table 4. i/o port alternate functions port name general purpose i/o pin no. alternate functions sdip56 tqfp64 p0.0 all ports useable for general pur- pose i/o (input, output or bidi- rectional) 14 8 i/o p0.1 13 7 i/o p0.2 12 6 i/o p0.3 11 5 ain0 i a/d analog data input 0 p0.4 10 4 ain4 i a/d analog data input 4 p0.5 9 3 ain5 i a/d analog data input 5 p0.6 8 2 ain6 i a/d analog data input 6 p0.7 7 63 ain7 i a/d analog data input 7 p2.0 36 34 ir i ifr infrared input int7 i external interrupt 7 p2.1 37 35 ain1 i a/d analog data input 1 int6 i external interrupt 6 p2.2 38 36 int3 i external interrupt 3 ain2 a/d analog data input 2 vso1 o voltage synthesis converter output 1 p2.3 39 37 int4 i external interrupt 4 ain3 i a/d analog data input 3 vso2 o voltage synthesis converter output 2 p2.4 3 59 int2 i external interrupt 2 scl1 i/o i 2 c channel 1 serial clock sck o spi serial clock output p2.5 4 60 sdio i/o spi serial data sda1 i/o i 2 c channel 1 serial data p2.6 5 61 nmi i non maskable interrupt input p2.7 6 62 int5 i external interrupt 5 pixclk o pixel clock (after divide-by-2) output p3.0 24 20 scl3 i/o i 2 c channel 3 serial clock tslu o translucency digital video output p3.1 23 19 sda3 i/o i 2 c channel 3 serial data p3.2 22 18 int0 i external interrupt 0 p3.3 21 15 syndet1 i sync error detector input 1 dsout2* o data slicer comparator output 2 p3.4 20 14 int1 i external interrupt 1 scl2 i/o i 2 c channel 2 serial clock touta* o mft timer output a p3.5 19 13 tina* i mft timer input a sda2 i/o i 2 c channel 2 serial data
15/268 general description * not available on some devices. p3.6 all ports useable for general pur- pose i/o (input, output or bidi- rectional) 18 12 syndet0 i sync error detector input 0 dsout1 o data slicer comparator output 1 p3.7 17 11 ccvideo2* i closed caption composite video input 1 (2v +/- 3 db) p4.0 43 41 scl4 i/o i 2 c channel 4 serial clock toutb* o mft timer output b pwm0 o pwm d/a converter output 0 p4.1 44 42 tinb* i mft timer input b sda4 i/o i 2 c channel 4 serial data pwm1 o pwm d/a converter output 1 p4.2 45 43 i/o p4.3 46 44 i/o p4.4 47 45 pwm4 o pwm d/a converter output 4 p4.5 48 46 pwm5 o pwm d/a converter output 5 p4.6 49 47 pwm6 o pwm d/a converter output 6 p4.7 50 50 extrg i a/d converter external trigger input pwm7 o pwm d/a converter output 7 p5.0 52 52 reseti o internal delayed reset output p5.1 53 53 sin0* i sci serial comm. interface input p5.2 54 54 sout0* o sci serial comm. interface output p5.5 1 57 pwm2 o pwm d/a converter output 2 p5.6 2 58 pwm3 o pwm d/a converter output 3 port name general purpose i/o pin no. alternate functions sdip56 tqfp64
16/268 general description 1.3 required external components v pp test0 p5.2/sout0* p5.1/sin0* p.5.0/reseti reset p4.7/pwm7/extrg p4.6/pwm6 p4.5/pwm5 p4.4/pwm4 p4.3 p4.2 p4.1/sda4/tinb*/pwm1 p4.0/scl4/toutb*/pwm0 oscin v ss2 oscout p2.3/ain3/vso2/int4 p2.2/ain2/vso1/int3 p2.1/ain1/int6 p2.0/ir/int7 hsync vsync fosd v dda fcpu v ss1 v dd1 pwm2/p5.5 pwm3/p5.6 sck/scl1/int2/p2.4 sdio/sda1/p2.5 nmi/p2.6 pixclk/int5/p2.7 ain7/p0.7 ain6/p0.6 ain5/p0.5 ain4/p0.4 ain0/p0.3 p0.2 p0.1 p0.0 ccvideo1 v dd2 ccvideo2*/p3.7 dsout1/syndet0/p3.6 tina*/sda2/p3.5 int1/touta*/scl2/p3.4 dsout2/syndet1/p3.3 int0/p3.2 sda3/p3.1 tslu/sdl3/p3.0 fb b g r 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 v dd (+5v) 270 10k 1mf sw-push v dd (+5v) gnd gnd gnd gnd 56pf 56pf 1m 4mhz osc. 1.2k 47nf gnd 1.2k 47nf 1f slicer 1 input 1f slicer 2 input (if present or used) + warning : the decoupling capacitors between analog and digital +5v (v dda , v dd1 , v dd2 ), and ground (v ss1 , v ss2 ) are not shown. add a 100nf and a 4.7f capacitor close to the corresponding pins if needed. 100pf 100pf
17/268 general description 1.4 memory map figure 4. st92196a memory map note 1: rom and ram sizes are product dependent, refer to the ordering information section on page 234 . 010000h segment 0 64 kbytes 00ffffh 00c000h 00bfffh 008000h 007fffh 004000h 000000h 003fffh page 0 - 16 kbytes page 1 - 16 kbytes page 2 - 16 kbytes page 3 - 16 kbytes segment 20h 64 kbytes 200000h 21ffffh 20c000h 20bfffh 208000h 207fffh 204000h 203fffh page 80 - 16 kbytes page 81 - 16 kbytes page 82 - 16 kbytes page 83 - 16 kbytes reserved segment 21h 64 kbytes 20ffffh 220000h 22ffffh 210000h segment 22h 64 kbytes segment 1 32 kbytes 017fffh 014000h 013fffh page 4 - 16 kbytes page 5 - 16 kbytes 220000h 22017fh 384 bytes osdram 128k bytes page 88 - 16 kbytes page 89 - 16 kbytes page 90 - 16 kbytes page 91 - 16 kbytes 22c000h 22bfffh 228000h 227fffh 224000h 223fffh 010000h 00ffffh 00c000h 00bfffh 008000h 007fffh 004000h 000000h 003fffh page 0 - 16 kbytes page 1 - 16 kbytes page 2 - 16 kbytes page 3 - 16 kbytes 200000h 21ffffh 20c000h 20bfffh 208000h 207fffh 204000h 203fffh page 80 - 16 kbytes page 81 - 16 kbytes page 82 - 16 kbytes page 83 - 16 kbytes reserved 20ffffh 220000h 210000h 017fffh 014000h 013fffh page 4 - 16 kbytes page 5 - 16 kbytes page 88 - 16 kbytes page 89 - 16 kbytes page 90 - 16 kbytes page 91 - 16 kbytes 22c000h 22bfffh 228000h 227fffh 224000h 223fffh 200000h 21ffffh 20c000h 20bfffh 208000h 207fffh 204000h 203fffh page 80 - 16 kbytes page 81 - 16 kbytes page 82 - 16 kbytes page 83 - 16 kbytes reserved 20ffffh 220000h 22ffffh 210000h page 88 - 16 kbytes page 89 - 16 kbytes page 90 - 16 kbytes page 91 - 16 kbytes 22c000h 22bfffh 228000h 227fffh 224000h 223fffh 200000h 21ffffh 20c000h 20bfffh 208000h 207fffh 204000h 203fffh page 80 - 16 kbytes page 81 - 16 kbytes page 82 - 16 kbytes page 83 - 16 kbytes reserved 20ffffh 220000h 210000h page 88 - 16 kbytes page 89 - 16 kbytes page 90 - 16 kbytes page 91 - 16 kbytes 22c000h 22bfffh 228000h 227fffh 224000h 223fffh 20fbffh 20f000h 20f3ffh 48 kbytes 1) 64 kbytes 1) 96 kbytes 1) internal rom 32k bytes 1) 000000h 00bfffh 007fffh 00ffffh 017fffh 20ffffh 4 kbytes 1) 3 kbytes 1) 2 kbytes 1) ram internal 1 kbyte 1) 20f7ffh
18/268 general description 1.5 st92196a register map table 6 contains the map of the group f peripheral pages. the common registers used by each peripheral are listed in table 5 . be very careful to correctly program both: C the set of registers dedicated to a particular function or peripheral. C registers common to other functions. C in particular, double-check that any registers with undefined reset values have been correct- ly initialised. warning : note that in the eivr and each ivr reg- ister, all bits are significant. take care when defin- ing base vector addresses that entries in the inter- rupt vector table do not overlap. table 5. common registers function or peripheral common registers sci, mft cicr + nicr + dma registers + i/o port registers adc cicr + nicr + i/o port registers wdt cicr + nicr + external interrupt registers + i/o port registers i/o ports i/o port registers + moder external interrupt interrupt registers + i/o port registers rccu interrupt registers + moder
19/268 general description st92196a register map (contd) table 6. group f pages register map resources available on the st92196a device: register page 0 2 3 9 101121244243444546555962 r255 res. res. res. res. mft res. mmu sci0 res. res. res. res. res. res. vs res. r254 spi port 3 tcc r253 res. r252 wcr osd res. pwm r251 wdt res. r250 port 2 ir/ sync err r249 r248 mft r247 ext int res. res. res. ds0 ds1 r246 port 5 rccu r245 res. i2c r244 r243 res. mft stim r242 port 0 port 4 adc r241 res. r240
20/268 general description st92196a register map (contd) table 7. detailed register map group f page dec. block reg. no. register name description reset value hex. doc. page n/a i/o port 0:5 r224 p0dr port 0 data register ff 69 r226 p2dr port 2 data register ff r227 p3dr port 3 data register ff r228 p4dr port 4 data register ff r229 p5dr port 5 data register ff core r230 cicr central interrupt control register 87 27 r231 flagr flag register 00 28 r232 rp0 pointer 0 register 00 30 r233 rp1 pointer 1 register 00 30 r234 ppr page pointer register 54 32 r235 moder mode register e0 32 r236 usphr user stack pointer high register xx 34 r237 usplr user stack pointer low register xx 34 r238 ssphr system stack pointer high reg. xx 34 r239 ssplr system stack pointer low reg. xx 34 0 int r242 eitr external interrupt trigger register 00 56 r243 eipr external interrupt pending reg. 00 56 r244 eimr external interrupt mask-bit reg. 00 56 r245 eiplr external interrupt priority level reg. ff 57 r246 eivr external interrupt vector register x6 57 r247 nicr nested interrupt control 00 57 wdt r248 wdthr watchdog timer high register ff 81 r249 wdtlr watchdog timer low register ff 81 r250 wdtpr watchdog timer prescaler reg. ff 81 r251 wdtcr watchdog timer control register 12 81 r252 wcr wait control register 7f 82 spi r253 spidr spi data register xx 190 r254 spicr spi control register 00 190 2 i/o port 0 r240 p0c0 port 0 configuration register 0 00 69 r241 p0c1 port 0 configuration register 1 00 r242 p0c2 port 0 configuration register 2 00 i/o port 2 r248 p2c0 port 2 configuration register 0 00 r249 p2c1 port 2 configuration register 1 00 r250 p2c2 port 2 configuration register 2 00 i/o port 3 r252 p3c0 port 3 configuration register 0 00 r253 p3c1 port 3 configuration register 1 00 r254 p3c2 port 3 configuration register 2 00
21/268 general description 3 i/o port 4 r240 p4c0 port 4 configuration register 0 00 69 r241 p4c1 port 4 configuration register 1 00 r242 p4c2 port 4 configuration register 2 00 i/o port 5 r244 p5c0 port 5 configuration register 0 00 r245 p5c1 port 5 configuration register 1 00 r246 p5c2 port 5 configuration register 2 00 9 mft r240 dcpr dma counter pointer register xx 108 r241 dapr dma address pointer register xx 109 r242 t_ivr interrupt vector register xx 109 r243 idcr interrupt/dma control register c7 110 r248 iocr i/o connection register fc 110 10 r240 reg0hr capture load register 0 high xx 101 r241 reg0lr capture load register 0 low xx 101 r242 reg1hr capture load register 1 high xx 101 r243 reg1lr capture load register 1 low xx 101 r244 cmp0hr compare 0 register high 00 101 r245 cmp0lr compare 0 register low 00 101 r246 cmp1hr compare 1 register high 00 101 r247 cmp1lr compare 1 register low 00 101 r248 tcr timer control register 0x 102 r249 tmr timer mode register 00 103 r250 t_icr external input control register 0x 104 r251 prsr prescaler register 00 104 r252 oacr output a control register xx 105 r253 obcr output b control register xx 106 r254 t_flagr flags register 00 107 r255 idmr interrupt/dma mask register 00 108 11 stim r240 sth counter high byte register ff 86 r241 stl counter low byte register ff 86 r242 stp standard timer prescaler register ff 86 r243 stc standard timer control register 14 86 21 mmu r240 dpr0 data page register 0 00 39 r241 dpr1 data page register 1 01 39 r242 dpr2 data page register 2 02 39 r243 dpr3 data page register 3 83 39 r244 csr code segment register 00 40 r248 isr interrupt segment register x0 40 r249 dmasr dma segment register x0 40 extmi r246 emr2 external memory register 2 0f 58 group f page dec. block reg. no. register name description reset value hex. doc. page
22/268 general description 24 sci0 r240 rdcpr receiver dma transaction counter pointer xx 201 r241 rdapr receiver dma source address pointer xx 201 r242 tdcpr transmitter dma transaction counter pointer xx 201 r243 tdapr transmitter dma destination address pointer xx 201 r244 s_ivr interrupt vector register xx 202 r245 acr address/data compare register xx 203 r246 imr interrupt mask register x0 203 r247 s_isr interrupt status register xx 204 r248 rxbr receive buffer register xx 205 r248 txbr transmitter buffer register xx 205 r249 idpr interrupt/dma priority register xx 206 r250 chcr character configuration register xx 207 r251 ccr clock configuration register 00 207 r252 brghr baud rate generator high reg. xx 208 r253 brglr baud rate generator low register xx 208 r254 sicr input control 03 208 r255 socr output control 01 208 42 osd r246 osdbcr2 border color register 2 x0 152 r247 osdbcr1 border color register 1 x0 152 r248 osder enable register 00 153 r249 osddr delay register xx 156 r250 osdfbr flag bit register xx 157 r251 osdslr scan line register xx 158 r252 osdmr mute register xx 158 43 ir/sync err r248 irpr infrared pulse register 00 169 r249 syncer sync error register 00 168 r250 irscr infrared / sync control register 00 168 tcc r253 mccr main clock control register 00 69 r254 skccr skew clock control register 00 69 44 i2c r240 i2coar own address register 00 175 r241 i2cfqr frequency register 00 176 r242 i2cctr control register 01 177 r243 i2cdr data register 00 178 r244 i2cstr2 status register 2 00 178 r245 i2cstr1 status register 1 00 179 group f page dec. block reg. no. register name description reset value hex. doc. page
23/268 general description note: xx denotes a byte with an undefined value, however some of the bits may have defined values. refer to register description for details. 45 ds0 r240 ds0dr1 data register 1 00 164 r241 ds0dr2 data register 2 00 164 r242 ds0dr3 data register 3 00 164 r243 ds0dr4 data register 4 00 165 r244 ds0cr1 control register 1 00 165 r245 ds0cr2 control register 2 00 165 r246 ds0mr monitor register 00 166 46 ds1 r240 ds1dr1 data register 1 00 164 r241 ds1dr2 data register 2 00 164 r242 ds1dr3 data register 3 00 164 r243 ds1dr4 data register 4 00 165 r244 ds1cr1 control register 1 00 165 r245 ds1cr2 control register 2 00 165 r246 ds1mr monitor register 00 166 55 rccu r240 clkctl clock control register 00 64 r242 clk_flag clock flag register 48, 28 or 08 64 59 pwm r240 cm0 compare register 0 00 216 r241 cm1 compare register 1 00 216 r242 cm2 compare register 2 00 216 r243 cm3 compare register 3 00 216 r244 cm4 compare register 4 00 216 r245 cm5 compare register 5 00 216 r246 cm6 compare register 6 00 216 r247 cm7 compare register 7 00 216 r248 acr autoclear register ff 217 r249 ccr counter register 00 217 r250 pctl prescaler and control register 0c 217 r251 ocpl output complement register 00 218 r252 oer output enable register 00 218 vs r254 vsdr1 data and control register 1 00 213 r255 vsdr2 data register 2 00 213 62 adc r240 addtr channel i data register xx 221 r241 adclr control logic register 00 221 r242 adint ad interrupt register 01 222 group f page dec. block reg. no. register name description reset value hex. doc. page
24/268 device architecture 2 device architecture 2.1 core architecture the st9 core or central processing unit (cpu) features a highly optimised instruction set, capable of handling bit, byte (8-bit) and word (16-bit) data, as well as bcd and boolean formats; 14 address- ing modes are available. four independent buses are controlled by the core: a 16-bit memory bus, an 8-bit register data bus, an 8-bit register address bus and a 6-bit in- terrupt/dma bus which connects the interrupt and dma controllers in the on-chip peripherals with the core. this multiple bus architecture affords a high de- gree of pipelining and parallel operation, thus mak- ing the st9 family devices highly efficient, both for numerical calculation, data handling and with re- gard to communication with on-chip peripheral re- sources. 2.2 memory spaces there are two separate memory spaces: C the register file, which comprises 240 8-bit registers, arranged as 15 groups (group 0 to e), each containing sixteen 8-bit registers plus up to 64 pages of 16 registers mapped in group f, which hold data and control bits for the on-chip peripherals and i/os. C a single linear memory space accommodating both program and data. all of the physically sep- arate memory areas, including the internal rom, internal ram and external memory are mapped in this common address space. the total ad- dressable memory space of 4 mbytes (limited by the size of on-chip memory and the number of external address pins) is arranged as 64 seg- ments of 64 kbytes. each segment is further subdivided into four pages of 16 kbytes, as illus- trated in figure 5 . a memory management unit uses a set of pointer registers to address a 22-bit memory field using 16-bit address-based instruc- tions. 2.2.1 register file the register file consists of (see figure 6 ): C 224 general purpose registers (group 0 to d, registers r0 to r223) C 6 system registers in the system group (group e, registers r224 to r239) C up to 64 pages, depending on device configura- tion, each containing up to 16 registers, mapped to group f (r240 to r255), see figure 7 . figure 5. single program and data memory address space 3fffffh 3f0000h 3effffh 3e0000h 20ffffh 02ffffh 020000h 01ffffh 010000h 00ffffh 000000h 8 7 6 5 4 3 2 1 0 63 62 2 1 0 address 16k pages 64k segments up to 4 mbytes data code 255 254 253 252 251 250 249 248 247 9 10 11 21ffffh 210000h 133 134 135 33 reserved 132
25/268 device architecture memory spaces (contd) figure 6. register groups figure 7. page pointer for group f mapping figure 8. addressing the register file f e d c b a 9 8 7 6 5 4 3 paged registers system registers 2 1 0 00 15 255 240 239 224 223 va00432 up to 64 pages general registers purpose 224 page 63 page 5 page 0 page pointer r255 r240 r224 r0 va00433 r234 register file system registers group d group b group c (1100) (0011) r192 r207 255 240 239 224 223 f e d c b a 9 8 7 6 5 4 3 2 1 0 15 vr000118 00 r195 r195 (r0c3h) paged registers
26/268 device architecture memory spaces (contd) 2.2.2 register addressing register file registers, including group f paged registers (but excluding group d), may be ad- dressed explicitly by means of a decimal, hexa- decimal or binary address; thus r231, re7h and r11100111b represent the same register (see figure 8 ). group d registers can only be ad- dressed in working register mode. note that an upper case r is used to denote this direct addressing mode. working registers certain types of instruction require that registers be specified in the form rx , where x is in the range 0 to 15: these are known as working regis- ters. note that a lower case r is used to denote this in- direct addressing mode. two addressing schemes are available: a single group of 16 working registers, or two separately mapped groups, each consisting of 8 working reg- isters. these groups may be mapped starting at any 8 or 16 byte boundary in the register file by means of dedicated pointer registers. this tech- nique is described in more detail in section 2.3.3, and illustrated in figure 9 and in figure 10 . system registers the 16 registers in group e (r224 to r239) are system registers and may be addressed using any of the register addressing modes. these registers are described in greater detail in section 2.3. paged registers up to 64 pages, each containing 16 registers, may be mapped to group f. these are addressed us- ing any register addressing mode, in conjunction with the page pointer register, r234, which is one of the system registers. this register selects the page to be mapped to group f and, once set, does not need to be changed if two or more regis- ters on the same page are to be addressed in suc- cession. therefore if the page pointer, r234, is set to 5, the instructions: spp #5 ld r242, r4 will load the contents of working register r4 into the third register of page 5 (r242). these paged registers hold data and control infor- mation relating to the on-chip peripherals, each peripheral always being associated with the same pages and registers to ensure code compatibility between st9 devices. the number of these regis- ters therefore depends on the peripherals which are present in the specific st9 family device. in other words, pages only exist if the relevant pe- ripheral is present. table 8. register file organization hex. address decimal address function register file group f0-ff 240-255 paged registers group f e0-ef 224-239 system registers group e d0-df 208-223 general purpose registers group d c0-cf 192-207 group c b0-bf 176-191 group b a0-af 160-175 group a 90-9f 144-159 group 9 80-8f 128-143 group 8 70-7f 112-127 group 7 60-6f 96-111 group 6 50-5f 80-95 group 5 40-4f 64-79 group 4 30-3f 48-63 group 3 20-2f 32-47 group 2 10-1f 16-31 group 1 00-0f 00-15 group 0
27/268 device architecture 2.3 system registers the system registers are listed in table 9 . they are used to perform all the important system set- tings. their purpose is described in the following pages. refer to the chapter dealing with i/o for a description of the port[5:0] data registers. table 9. system registers (group e) 2.3.1 central interrupt control register please refer to the interrupt chapter for a de- tailed description of the st9 interrupt philosophy. central interrupt control register (cicr) r230 - read/write register group: e (system) reset value: 1000 0111 (87h) bit 7 = gcen : global counter enable . this bit is the global counter enable of the multi- function timers. the gcen bit is anded with the ce bit in the tcr register (only in devices featur- ing the mft multifunction timer) in order to enable the timers when both bits are set. this bit is set af- ter the reset cycle. note: if an mft is not included in the st9 device, then this bit has no effect. bit 6 = tlip : top level interrupt pending . this bit is set by hardware when a top level inter- rupt request is recognized. this bit can also be set by software to simulate a top level interrupt request. 0: no top level interrupt pending 1: top level interrupt pending bit 5 = tli : top level interrupt bit . 0: top level interrupt is acknowledged depending on the tlnm bit in the nicr register. 1: top level interrupt is acknowledged depending on the ien and tlnm bits in the nicr register (described in the interrupt chapter). bit 4 = ien : interrupt enable . this bit is cleared by interrupt acknowledgement, and set by interrupt return ( iret ). ien is modified implicitly by iret , ei and di instructions or by an interrupt acknowledge cycle. it can also be explic- itly written by the user, but only when no interrupt is pending. therefore, the user should execute a di instruction (or guarantee by other means that no interrupt request can arrive) before any write operation to the cicr register. 0: disable all interrupts except top level interrupt. 1: enable interrupts bit 3 = iam : interrupt arbitration mode . this bit is set and cleared by software to select the arbitration mode. 0: concurrent mode 1: nested mode. bits 2:0 = cpl[2:0] : current priority level . these three bits record the priority level of the rou- tine currently running (i.e. the current priority lev- el, cpl). the highest priority level is represented by 000, and the lowest by 111. the cpl bits can be set by hardware or software and provide the reference according to which subsequent inter- rupts are either left pending or are allowed to inter- rupt the current interrupt service routine. when the current interrupt is replaced by one of a higher pri- ority, the current priority value is automatically stored until required in the nicr register. r239 (efh) ssplr r238 (eeh) ssphr r237 (edh) usplr r236 (ech) usphr r235 (ebh) mode register r234 (eah) page pointer register r233 (e9h) register pointer 1 r232 (e8h) register pointer 0 r231 (e7h) flag register r230 (e6h) central int. cntl reg r229 (e5h) port5 data reg. r228 (e4h) port4 data reg. r227 (e3h) port3 data reg. r226 (e2h) port2 data reg. r225 (e1h) port1 data reg. r224 (e0h) port0 data reg. 70 gcen tlip tli ien iam cpl2 cpl1 cpl0
28/268 device architecture system registers (contd) 2.3.2 flag register the flag register contains 8 flags which indicate the cpu status. during an interrupt, the flag regis- ter is automatically stored in the system stack area and recalled at the end of the interrupt service rou- tine, thus returning the cpu to its original status. this occurs for all interrupts and, when operating in nested mode, up to seven versions of the flag register may be stored. flag register (flagr) r231- read/write register group: e (system) reset value: 0000 0000 (00h ) bit 7 = c : carry flag . the carry flag is affected by: addition ( add, addw, adc, adcw ), subtraction ( sub, subw, sbc, sbcw ), compare ( cp, cpw ), shift right arithmetic ( sra, sraw ), shift left arithmetic ( sla, slaw ), swap nibbles ( swap ), rotate ( rrc, rrcw, rlc, rlcw, ror, rol ), decimal adjust ( da ), multiply and divide ( mul, div, divws ). when set, it generally indicates a carry out of the most significant bit position of the register being used as an accumulator (bit 7 for byte operations and bit 15 for word operations). the carry flag can be set by the set carry flag ( scf ) instruction, cleared by the reset carry flag ( rcf ) instruction, and complemented by the com- plement carry flag ( ccf ) instruction. bit 6 = z: zero flag . the zero flag is affected by: addition ( add, addw, adc, adcw ), subtraction ( sub, subw, sbc, sbcw ), compare ( cp, cpw ), shift right arithmetic ( sra, sraw ), shift left arithmetic ( sla, slaw ), swap nibbles ( swap ), rotate (rrc , rrcw, rlc, rlcw, ror, rol) , decimal adjust ( da ), multiply and divide ( mul, div, divws ), logical ( and, andw, or, orw, xor, xorw, cpl ), increment and decrement ( inc, incw, dec, decw ), test ( tm, tmw, tcm, tcmw, btset ). in most cases, the zero flag is set when the contents of the register being used as an accumulator be- come zero, following one of the above operations. bit 5 = s : sign flag . the sign flag is affected by the same instructions as the zero flag. the sign flag is set when bit 7 (for a byte opera- tion) or bit 15 (for a word operation) of the register used as an accumulator is one. bit 4 = v : overflow flag . the overflow flag is affected by the same instruc- tions as the zero and sign flags. when set, the overflow flag indicates that a two's- complement number, in a result register, is in er- ror, since it has exceeded the largest (or is less than the smallest), number that can be represent- ed in twos-complement notation. bit 3 = da : decimal adjust flag . the da flag is used for bcd arithmetic. since the algorithm for correcting bcd operations is differ- ent for addition and subtraction, this flag is used to specify which type of instruction was executed last, so that the subsequent decimal adjust ( da ) operation can perform its function correctly. the da flag cannot normally be used as a test condi- tion by the programmer. bit 2 = h : half carry flag. the h flag indicates a carry out of (or a borrow in- to) bit 3, as the result of adding or subtracting two 8-bit bytes, each representing two bcd digits. the h flag is used by the decimal adjust ( da ) instruc- tion to convert the binary result of a previous addi- tion or subtraction into the correct bcd result. like the da flag, this flag is not normally accessed by the user. bit 1 = reserved bit (must be 0). bit 0 = dp : data/program memory flag . this bit indicates the memory area addressed. its value is affected by the set data memory ( sdm ) and set program memory ( spm ) instructions. re- fer to the memory management unit for further de- tails. 70 c z s v da h - dp
29/268 device architecture system registers (contd) if the bit is set, data is accessed using the data pointers (dprs registers), otherwise it is pointed to by the code pointer (csr register); therefore, the user initialization routine must include a sdm instruction. note that code is always pointed to by the code pointer (csr). note: in the current st9 devices, the dp flag is only for compatibility with software developed for the first generation of st9 devices. with the single memory addressing space, its use is now redun- dant. it must be kept to 1 with a sdm instruction at the beginning of the program to ensure a normal use of the different memory pointers. 2.3.3 register pointing techniques two registers within the system register group, are used as pointers to the working registers. reg- ister pointer 0 (r232) may be used on its own as a single pointer to a 16-register working space, or in conjunction with register pointer 1 (r233), to point to two separate 8-register spaces. for the purpose of register pointing, the 16 register groups of the register file are subdivided into 32 8- register blocks. the values specified with the set register pointer instructions refer to the blocks to be pointed to in twin 8-register mode, or to the low- er 8-register block location in single 16-register mode. the set register pointer instructions srp , srp0 and srp1 automatically inform the cpu whether the register file is to operate in single 16-register mode or in twin 8-register mode. the srp instruc- tion selects the single 16-register group mode and specifies the location of the lower 8-register block, while the srp0 and srp1 instructions automatical- ly select the twin 8-register group mode and spec- ify the locations of each 8-register block. there is no limitation on the order or position of these register groups, other than that they must start on an 8-register boundary in twin 8-register mode, or on a 16-register boundary in single 16- register mode. the block number should always be an even number in single 16-register mode. the 16-regis- ter group will always start at the block whose number is the nearest even number equal to or lower than the block number specified in the srp instruction. avoid using odd block numbers, since this can be confusing if twin mode is subsequently selected. thus: srp #3 will be interpreted as srp #2 and will al- low using r16 ..r31 as r0 .. r15. in single 16-register mode, the working registers are referred to as r0 to r15 . in twin 8-register mode, registers r0 to r7 are in the block pointed to by rp0 (by means of the srp0 instruction), while registers r8 to r15 are in the block pointed to by rp1 (by means of the srp1 instruction). caution : group d registers can only be accessed as working registers using the register pointers, or by means of the stack pointers. they cannot be addressed explicitly in the form rxxx .
30/268 device architecture system registers (contd) pointer 0 register (rp0) r232 - read/write register group: e (system) reset value: xxxx xx00 (xxh) bits 7:3 = rg[4:0] : register group number. these bits contain the number (in the range 0 to 31) of the register block specified in the srp0 or srp instructions. in single 16-register mode the number indicates the lower of the two 8-register blocks to which the 16 working registers are to be mapped, while in twin 8-register mode it indicates the 8-register block to which r0 to r7 are to be mapped. bit 2 = rps : register pointer selector . this bit is set by the instructions srp0 and srp1 to indicate that the twin register pointing mode is se- lected. the bit is reset by the srp instruction to in- dicate that the single register pointing mode is se- lected. 0: single register pointing mode 1: twin register pointing mode bits 1:0: reserved. forced by hardware to zero. pointer 1 register (rp1) r233 - read/write register group: e (system) reset value: xxxx xx00 (xxh) this register is only used in the twin register point- ing mode. when using the single register pointing mode, or when using only one of the twin register groups, the rp1 register must be considered as reserved and may not be used as a general purpose register. bits 7:3 = rg[4:0]: register group number. these bits contain the number (in the range 0 to 31) of the 8-register block specified in the srp1 in- struction, to which r8 to r15 are to be mapped. bit 2 = rps : register pointer selector . this bit is set by the srp0 and srp1 instructions to indicate that the twin register pointing mode is se- lected. the bit is reset by the srp instruction to in- dicate that the single register pointing mode is se- lected. 0: single register pointing mode 1: twin register pointing mode bits 1:0: reserved. forced by hardware to zero. 70 rg4 rg3 rg2 rg1 rg0 rps 0 0 70 rg4 rg3 rg2 rg1 rg0 rps 0 0
31/268 device architecture system registers (contd) figure 9. pointing to a single group of 16 registers figure 10. pointing to two groups of 8 registers 31 30 29 28 27 26 25 9 8 7 6 5 4 3 2 1 0 f e d 4 3 2 1 0 block number register group register file register pointer 0 srp #2 set by: instruction points to: group 1 addressed by block 2 r15 r0 31 30 29 28 27 26 25 9 8 7 6 5 4 3 2 1 0 f e d 4 3 2 1 0 block number register group register file register pointer 0 srp0 #2 set by: instructions point to: group 1 addressed by block 2 & register pointer 1 srp1 #7 & group 3 addressed by block 7 r7 r0 r15 r8
32/268 device architecture system registers (contd) 2.3.4 paged registers up to 64 pages, each containing 16 registers, may be mapped to group f. these paged registers hold data and control information relating to the on-chip peripherals, each peripheral always being associated with the same pages and registers to ensure code compatibility between st9 devices. the number of these registers depends on the pe- ripherals present in the specific st9 device. in oth- er words, pages only exist if the relevant peripher- al is present. the paged registers are addressed using the nor- mal register addressing modes, in conjunction with the page pointer register, r234, which is one of the system registers. this register selects the page to be mapped to group f and, once set, does not need to be changed if two or more regis- ters on the same page are to be addressed in suc- cession. thus the instructions: spp #5 ld r242, r4 will load the contents of working register r4 into the third register of page 5 (r242). warning: during an interrupt, the ppr register is not saved automatically in the stack. if needed, it should be saved/restored by the user within the in- terrupt routine. page pointer register (ppr) r234 - read/write register group: e (system) reset value: xxxx xx00 (xxh ) bits 7:2 = pp[5:0] : page pointer . these bits contain the number (in the range 0 to 63) of the page specified in the spp instruction. once the page pointer has been set, there is no need to refresh it unless a different page is re- quired. bits 1:0: reserved. forced by hardware to 0. 2.3.5 mode register the mode register allows control of the following operating parameters: C selection of internal or external system and user stack areas, C management of the clock frequency, C enabling of bus request and wait signals when interfacing to external memory. mode register (moder) r235 - read/write register group: e (system) reset value: 1110 0000 (e0h) bit 7 = ssp : system stack pointer . this bit selects an internal or external system stack area. 0: external system stack area, in memory space. 1: internal system stack area, in the register file (reset state). bit 6 = usp : user stack pointer . this bit selects an internal or external user stack area. 0: external user stack area, in memory space. 1: internal user stack area, in the register file (re- set state). bit 5 = div2 : crystal oscillator clock divided by 2 . this bit controls the divide-by-2 circuit operating on the crystal oscillator clock (clock1). 0: clock divided by 1 1: clock divided by 2 bits 4:2 = prs[2:0] : cpuclk prescaler . these bits load the prescaler division factor for the internal clock (intclk). the prescaler factor se- lects the internal clock frequency, which can be di- vided by a factor from 1 to 8. refer to the reset and clock control chapter for further information. bit 1 = brqen : bus request enable . 0: external memory bus request disabled 1: external memory bus request enabled on breq pin (where available). note: disregard this bit if breq pin is not availa- ble. bit 0 = himp : high impedance enable . when any of ports 0, 1, 2 or 6 depending on de- vice configuration, are programmed as address and data lines to interface external memory, these lines and the memory interface control lines (as, ds, r/w) can be forced into the high impedance 70 pp5 pp4 pp3 pp2 pp1 pp0 0 0 70 ssp usp div2 prs2 prs1 prs0 brqen himp
33/268 device architecture system registers (contd) state by setting the himp bit. when this bit is reset, it has no effect. setting the himp bit is recommended for noise re- duction when only internal memory is used. if port 1 and/or 2 are declared as an address and as an i/o port (for example: p10... p14 = address, and p15... p17 = i/o), the himp bit has no effect on the i/o lines. 2.3.6 stack pointers two separate, double-register stack pointers are available: the system stack pointer and the user stack pointer, both of which can address registers or memory. the stack pointers point to the bottom of the stacks which are f illed using the push commands and emptied using the pop commands. the stack pointer is automatically pre-decremented when data is pushed in and post-incremented when data is popped out. the push and pop commands used to manage the system stack may be addressed to the user stack by adding the suffix u . to use a stack in- struction for a word, the suffix w is added. these suffixes may be combined. when bytes (or words) are popped out from a stack, the contents of the stack locations are un- changed until fresh data is loaded. thus, when data is popped from a stack area, the stack con- tents remain unchanged. note: instructions such as: pushuw rr236 or pushw rr238, as well as the corresponding pop instructions (where r236 & r237, and r238 & r239 are themselves the user and system stack pointers respectively), must not be used, since the pointer values are themselves automatically changed by the push or pop instruction, thus cor- rupting their value. system stack the system stack is used for the temporary stor- age of system and/or control data, such as the flag register and the program counter. the following automatically push data onto the system stack: C interrupts when entering an interrupt, the pc and the flag register are pushed onto the system stack. if the encsr bit in the emr2 register is set, then the code segment register is also pushed onto the system stack. C subroutine calls when a call instruction is executed, only the pc is pushed onto stack, whereas when a calls in- struction (call segment) is executed, both the pc and the code segment register are pushed onto the system stack. C link instruction the link or linku instructions create a c lan- guage stack frame of user-defined length in the system or user stack. all of the above conditions are associated with their counterparts, such as return instructions, which pop the stored data items off the stack. user stack the user stack provides a totally user-controlled stacking area. the user stack pointer consists of two registers, r236 and r237, which are both used for address- ing a stack in memory. when stacking in the reg- ister file, the user stack pointer high register, r236, becomes redundant but must be consid- ered as reserved. stack pointers both system and user stacks are pointed to by double-byte stack pointers. stacks may be set up in ram or in the register file. only the lower byte will be required if the stack is in the register file. the upper byte must then be considered as re- served and must not be used as a general purpose register. the stack pointer registers are located in the sys- tem group of the register file, this is illustrated in table 9 . stack location care is necessary when managing stacks as there is no limit to stack sizes apart from the bottom of any address space in which the stack is placed. consequently programmers are advised to use a stack pointer value as high as possible, particular- ly when using the register file as a stacking area. group d is a good location for a stack in the reg- ister file, since it is the highest available area. the stacks may be located anywhere in the first 14 groups of the register file (internal stacks) or in ram (external stacks). note . stacks must not be located in the paged register group or in the system register group.
34/268 device architecture system registers (contd) user stack pointer high register (usphr) r236 - read/write register group: e (system) reset value: undefined user stack pointer low register (usplr) r237 - read/write register group: e (system) reset value: undefined figure 11. internal stack mode system stack pointer high register (ssphr) r238 - read/write register group: e (system) reset value: undefined system stack pointer low register (ssplr) r239 - read/write register group: e (system) reset value: undefined figure 12. external stack mode 70 usp15 usp14 usp13 usp12 usp11 usp10 usp9 usp8 70 usp7 usp6 usp5 usp4 usp3 usp2 usp1 usp0 f e d 4 3 2 1 0 register file stack pointer (low) points to: stack 70 ssp15 ssp14 ssp13 ssp12 ssp11 ssp10 ssp9 ssp8 70 ssp7 ssp6 ssp5 ssp4 ssp3 ssp2 ssp1 ssp0 f e d 4 3 2 1 0 register file stack pointer (low) point to: stack memory stack pointer (high) &
35/268 device architecture 2.4 memory organization code and data are accessed within the same line- ar address space. all of the physically separate memory areas, including the internal rom, inter- nal ram and external memory are mapped in a common address space. the st9 provides a total addressable memory space of 4 mbytes. this address space is ar- ranged as 64 segments of 64 kbytes; each seg- ment is again subdivided into four 16 kbyte pages. the mapping of the various memory areas (inter- nal ram or rom, external memory) differs from device to device. each 64-kbyte physical memory segment is mapped either internally or externally; if the memory is internal and smaller than 64 kbytes, the remaining locations in the 64-kbyte segment are not used (reserved). refer to the register and memory map chapter for more details on the memory map.
36/268 device architecture 2.5 memory management unit the cpu core includes a memory management unit (mmu) which must be programmed to per- form memory accesses (even if external memory is not used). the mmu is controlled by 7 registers and 2 bits (encsr and dprrem) present in emr2, which may be written and read by the user program. these registers are mapped within group f, page 21 of the register file. the 7 registers may be sub-divided into 2 main groups: a first group of four 8-bit registers (dpr[3:0]), and a second group of three 6-bit registers (csr, isr, and dmasr). the first group is used to extend the address during data memory access (dpr[3:0]). the second is used to manage program and data memory ac- cesses during code execution (csr), interrupts service routines (isr or csr), and dma trans- fers (dmasr or isr). figure 13. page 21 registers dmasr isr emr2 emr1 csr dpr3 dpr2 dpr1 dpr0 r255 r254 r253 r252 r251 r250 r249 r248 r247 r246 r245 r244 r243 r242 r241 r240 ffh feh fdh fch fbh fah f9h f8h f7h f6h f5h f4h f3h f2h f1h f0h mmu em page 21 mmu mmu bit dprrem=0 ssplr ssphr usplr usphr moder ppr rp1 rp0 flagr cicr p5dr p4dr p3dr p2dr p1dr p0dr dmasr isr emr2 emr1 csr dpr3 dpr2 1 dpr0 bit dprrem=1 ssplr ssphr usplr usphr moder ppr rp1 rp0 flagr cicr p5dr p4dr p3dr p2dr p1dr p0dr dmasr isr emr2 emr1 csr dpr3 dpr2 dpr1 dpr0 relocation of p[3:0] and dpr[3:0] registers (default setting)
37/268 device architecture 2.6 address space extension to manage 4 mbytes of addressing space, it is necessary to have 22 address bits. the mmu adds 6 bits to the usual 16-bit address, thus trans- lating a 16-bit virtual address into a 22-bit physical address. there are 2 different ways to do this de- pending on the memory involved and on the oper- ation being performed. 2.6.1 addressing 16-kbyte pages this extension mode is implicitly used to address data memory space if no dma is being performed. the data memory space is divided into 4 pages of 16 kbytes. each one of the four 8-bit registers (dpr[3:0], data page registers) selects a differ- ent 16-kbyte page. the dpr registers allow ac- cess to the entire memory space which contains 256 pages of 16 kbytes. data paging is performed by extending the 14 lsb of the 16-bit address with the contents of a dpr register. the two msbs of the 16-bit address are interpreted as the identification number of the dpr register to be used. therefore, the dpr registers are involved in the following virtual address rang- es: dpr0: from 0000h to 3fffh; dpr1: from 4000h to 7fffh; dpr2: from 8000h to bfffh; dpr3: from c000h to ffffh. the contents of the selected dpr register specify one of the 256 possible data memory pages. this 8-bit data page number, in addition to the remain- ing 14-bit page offset address forms the physical 22-bit address (see figure 14 ). a dpr register cannot be modified via an address- ing mode that uses the same dpr register. for in- stance, the instruction popw dpr0 is legal only if the stack is kept either in the register file or in a memory location above 8000h, where dpr2 and dpr3 are used. otherwise, since dpr0 and dpr1 are modified by the instruction, unpredicta- ble behaviour could result. figure 14. addressing via dpr[3:0] dpr0 dpr1 dpr2 dpr3 00 01 10 11 16-bit virtual address 22-bit physical address 8 bits mmu registers 2 m sb 14 lsb
38/268 device architecture address space extension (contd) 2.6.2 addressing 64-kbyte segments this extension mode is used to address data memory space during a dma and program mem- ory space during any code execution (normal code and interrupt routines). three registers are used: csr, isr, and dmasr. the 6-bit contents of one of the registers csr, isr, or dmasr define one out of 64 memory seg- ments of 64 kbytes within the 4 mbytes address space. the register contents represent the 6 msbs of the memory address, whereas the 16 lsbs of the address (intra-segment address) are given by the virtual 16-bit address (see figure 15 ). 2.7 mmu registers the mmu uses 7 registers mapped into group f, page 21 of the register file and 2 bits of the emr2 register. most of these registers do not have a default value after reset. 2.7.1 dpr[3:0]: data page registers the dpr[3:0] registers allow access to the entire 4 mbyte memory space composed of 256 pages of 16 kbytes. 2.7.1.1 data page register relocation if these registers are to be used frequently, they may be relocated in register group e, by program- ming bit 5 of the emr2-r246 register in page 21. if this bit is set, the dpr[3:0] registers are located at r224-227 in place of the port 0-3 data registers, which are re-mapped to the default dpr's loca- tions: r240-243 page 21. data page register relocation is illustrated in fig- ure 13 . figure 15. addressing via csr, isr, and dmasr fetching program data memory fetching interrupt instruction accessed in dma instruction or dma access to program memory 16-bit virtual address 22-bit physical address 6 bits mmu registers csr isr dmasr 1 2 3 1 2 3
39/268 device architecture mmu registers (contd) data page register 0 (dpr0) r240 - read/write register page: 21 reset value: undefined this register is relocated to r224 if emr2.5 is set. bits 7:0 = dpr0_[7:0] : these bits define the 16- kbyte data memory page number. they are used as the most significant address bits (a21-14) to ex- tend the address during a data memory access. the dpr0 register is used when addressing the virtual address range 0000h-3fffh. data page register 1 (dpr1) r241 - read/write register page: 21 reset value: undefined this register is relocated to r225 if emr2.5 is set. bits 7:0 = dpr1_[7:0] : these bits define the 16- kbyte data memory page number. they are used as the most significant address bits (a21-14) to ex- tend the address during a data memory access. the dpr1 register is used when addressing the virtual address range 4000h-7fffh. data page register 2 (dpr2) r242 - read/write register page: 21 reset value: undefined this register is relocated to r226 if emr2.5 is set. bits 7:0 = dpr2_[7:0] : these bits define the 16- kbyte data memory page. they are used as the most significant address bits (a21-14) to extend the address during a data memory access. the dpr2 register is involved when the virtual address is in the range 8000h-bfffh. data page register 3 (dpr3) r243 - read/write register page: 21 reset value: undefined this register is relocated to r227 if emr2.5 is set. bits 7:0 = dpr3_[7:0] : these bits define the 16- kbyte data memory page. they are used as the most significant address bits (a21-14) to extend the address during a data memory access. the dpr3 register is involved when the virtual address is in the range c000h-ffffh. 70 dpr0_7 dpr0_6 dpr0_5 dpr0_4 dpr0_3 dpr0_2 dpr0_1 dpr0_0 70 dpr1_7 dpr1_6 dpr1_5 dpr1_4 dpr1_3 dpr1_2 dpr1_1 dpr1_0 70 dpr2_7 dpr2_6 dpr2_5 dpr2_4 dpr2_3 dpr2_2 dpr2_1 dpr2_0 70 dpr3_7 dpr3_6 dpr3_5 dpr3_4 dpr3_3 dpr3_2 dpr3_1 dpr3_0
40/268 device architecture mmu registers (contd) 2.7.2 csr: code segment register this register selects the 64-kbyte code segment being used at run-time to access instructions. it can also be used to access data if the spm instruc- tion has been executed (or ldpp, ldpd, lddp ). only the 6 lsbs of the csr register are imple- mented, and bits 6 and 7 are reserved. the csr register allows access to the entire memory space, divided into 64 segments of 64 kbytes. to generate the 22-bit program memory address, the contents of the csr register is directly used as the 6 msbs, and the 16-bit virtual address as the 16 lsbs. note: the csr register should only be read and not written for data operations (there are some ex- ceptions which are documented in the following paragraph). it is, however, modified either directly by means of the jps and calls instructions, or indirectly via the stack, by means of the rets in- struction. code segment register (csr) r244 - read/write register page: 21 reset value: 0000 0000 (00h) bits 7:6 = reserved, keep in reset state. bits 5:0 = csr_[5:0] : these bits define the 64- kbyte memory segment (among 64) which con- tains the code being executed. these bits are used as the most significant address bits (a21-16). 2.7.3 isr: interrupt segment register interrupt segment register (isr) r248 - read/write register page: 21 reset value: undefined isr and encsr bit (emr2 register) are also de- scribed in the chapter relating to interrupts, please refer to this description for further details. bits 7:6 = reserved, keep in reset state. bits 5:0 = isr_[5:0] : these bits define the 64- kbyte memory segment (among 64) which con- tains the interrupt vector table and the code for in- terrupt service routines and dma transfers (when the ps bit of the dapr register is reset). these bits are used as the most significant address bits (a21-16). the isr is used to extend the address space in two cases: C whenever an interrupt occurs: isr points to the 64-kbyte memory segment containing the inter- rupt vector table and the interrupt service routine code. see also the interrupts chapter. C during dma transactions between the peripheral and memory when the ps bit of the dapr regis- ter is reset : isr points to the 64 k-byte memory segment that will be involved in the dma trans- action. 2.7.4 dmasr: dma segment register dma segment register (dmasr) r249 - read/write register page: 21 reset value: undefined bits 7:6 = reserved, keep in reset state. bits 5:0 = dmasr_[5:0] : these bits define the 64- kbyte memory segment (among 64) used when a dma transaction is performed between the periph- eral's data register and memory, with the ps bit of the dapr register set. these bits are used as the most significant address bits (a21-16). if the ps bit is reset, the isr register is used to extend the ad- dress. 70 00 csr_5 csr_4 csr_3 csr_2 csr_1 csr_0 70 0 0 isr_5 isr_4 isr_3 isr_2 isr_1 isr_0 70 00 dma sr_5 dma sr_4 dma sr_3 dma sr_2 dma sr_1 dma sr_0
41/268 device architecture mmu registers (contd) figure 16. memory addressing scheme (example) 3fffffh 294000h 240000h 23ffffh 20c000h 200000h 1fffffh 040000h 03ffffh 030000h 020000h 010000h 00c000h 000000h dmasr isr csr dpr3 dpr2 dpr1 dpr0 4m bytes 16k 16k 16k 64k 64k 64k 16k
42/268 device architecture 2.8 mmu usage 2.8.1 normal program execution program memory is organized as a set of 64- kbyte segments. the program can span as many segments as needed, but a procedure cannot stretch across segment boundaries. jps , calls and rets instructions, which automatically modify the csr, must be used to jump across segment boundaries. writing to the csr is forbidden during normal program execution because it is not syn- chronized with the opcode fetch. this could result in fetching the first byte of an instruction from one memory segment and the second byte from anoth- er. writing to the csr is allowed when it is not be- ing used, i.e during an interrupt service routine if encsr is reset. note that a routine must always be called in the same way, i.e. either always with call or always with calls , depending on whether the routine ends with ret or rets . this means that if the rou- tine is written without prior knowledge of the loca- tion of other routines which call it, and all the pro- gram code does not fit into a single 64-kbyte seg- ment, then calls / rets should be used. in typical microcontroller applications, less than 64 kbytes of ram are used, so the four data space pages are normally sufficient, and no change of dpr[3:0] is needed during program execution. it may be useful however to map part of the rom into the data space if it contains strings, tables, bit maps, etc. if there is to be frequent use of paging, the user can set bit 5 (dprrem) in register r246 (emr2) of page 21. this swaps the location of registers dpr[3:0] with that of the data registers of ports 0- 3. in this way, dpr registers can be accessed without the need to save/set/restore the page pointer register. port registers are therefore moved to page 21. applications that require a lot of paging typically use more than 64 kbytes of exter- nal memory, and as ports 0, 1 and 2 are required to address it, their data registers are unused. 2.8.2 interrupts the isr register has been created so that the in- terrupt routines may be found by means of the same vector table even after a segment jump/call. when an interrupt occurs, the cpu behaves in one of 2 ways, depending on the value of the enc- sr bit in the emr2 register (r246 on page 21). if this bit is reset (default condition), the cpu works in original st9 compatibility mode. for the duration of the interrupt service routine, the isr is used instead of the csr, and the interrupt stack frame is kept exactly as in the original st9 (only the pc and flags are pushed). this avoids the need to save the csr on the stack in the case of an interrupt, ensuring a fast interrupt response time. the drawback is that it is not possible for an interrupt service routine to perform segment calls / jps : these instructions would update the csr, which, in this case, is not used (isr is used instead). the code size of all interrupt service rou- tines is thus limited to 64 kbytes. if, instead, bit 6 of the emr2 register is set, the isr is used only to point to the interrupt vector ta- ble and to initialize the csr at the beginning of the interrupt service routine: the old csr is pushed onto the stack together with the pc and the flags, and then the csr is loaded with the isr. in this case, an iret will also restore the csr from the stack. this approach lets interrupt service routines access the whole 4-mbyte address space. the drawback is that the interrupt response time is slightly increased, because of the need to also save the csr on the stack. compatibility with the original st9 is also lost in this case, because the interrupt stack frame is different; this difference, however, would not be noticeable for a vast major- ity of programs. data memory mapping is independent of the value of bit 6 of the emr2 register, and remains the same as for normal code execution: the stack is the same as that used by the main program, as in the st9. if the interrupt service routine needs to access additional data memory, it must save one (or more) of the dprs, load it with the needed memory page and restore it before completion. 2.8.3 dma depending on the ps bit in the dapr register (see dma chapter) dma uses either the isr or the dmasr for memory accesses: this guarantees that a dma will always find its memory seg- ment(s), no matter what segment changes the ap- plication has performed. unlike interrupts, dma transactions cannot save/restore paging registers, so a dedicated segment register (dmasr) has been created. having only one register of this kind means that all dma accesses should be pro- grammed in one of the two following segments: the one pointed to by the isr (when the ps bit of the dapr register is reset), and the one refer- enced by the dmasr (when the ps bit is set).
43/268 interrupts 3 interrupts 3.1 introduction the st9 responds to peripheral and external events through its interrupt channels. current pro- gram execution can be suspended to allow the st9 to execute a specific response routine when such an event occurs, providing that interrupts have been enabled, and according to a priority mechanism. if an event generates a valid interrupt request, the current program status is saved and control passes to the appropriate interrupt service routine. the st9 cpu can receive requests from the fol- lowing sources: C on-chip peripherals C external pins C top-level pseudo-non-maskable interrupt according to the on-chip peripheral features, an event occurrence can generate an interrupt re- quest which depends on the selected mode. up to eight external interrupt channels, with pro- grammable input trigger edge, are available. in ad- dition, a dedicated interrupt channel, set to the top-level priority, can be devoted either to the ex- ternal nmi pin (where available) to provide a non- maskable interrupt, or to the timer/watchdog. in- terrupt service routines are addressed through a vector table mapped in memory. figure 17. interrupt response n normal program flow interrupt service routine iret instruction interrupt vr001833 clear pending bit
44/268 interrupts 3.2 interrupt vectoring the st9 implements an interrupt vectoring struc- ture which allows the on-chip peripheral to identify the location of the first instruction of the interrupt service routine automatically. when an interrupt request is acknowledged, the peripheral interrupt module provides, through its interrupt vector register (ivr), a vector to point into the vector table of locations containing the start addresses of the interrupt service routines (defined by the programmer). each peripheral has a specific ivr mapped within its register file pages. the interrupt vector table, containing the address- es of the interrupt service routines, is located in the first 256 locations of memory pointed to by the isr register, thus allowing 8-bit vector addressing. for a description of the isr register refer to the chapter describing the mmu. the user power on reset vector is stored in the first two physical bytes in memory, 000000h and 000001h. the top level interrupt vector is located at ad- dresses 0004h and 0005h in the segment pointed to by the interrupt segment register (isr). with one interrupt vector register, it is possible to address several interrupt service routines; in fact, peripherals can share the same interrupt vector register among several interrupt channels. the most significant bits of the vector are user pro- grammable to define the base vector address with- in the vector table, the least significant bits are controlled by the interrupt module, in hardware, to select the appropriate vector. note : the first 256 locations of the memory seg- ment pointed to by isr can contain program code. 3.2.1 divide by zero trap the divide by zero trap vector is located at ad- dresses 0002h and 0003h of each code segment; it should be noted that for each code segment a divide by zero service routine is required. warning . although the divide by zero trap oper- ates as an interrupt, the flag register is not pushed onto the system stack automatically. as a result it must be regarded as a subroutine, and the service routine must end with the ret instruction (not iret ). user isr program memory power-on reset divide-by-zero top level int. lo lo lo hi hi hi 000000h user main program user top level isr user divide-by-zero isr 0000ffh vector table isr address even odd int. vector register lo hi register file r240 r239 f page registers 000002h 000004h
45/268 interrupts 3.2.2 segment paging during interrupt routines the encsr bit in the emr2 register can be used to select between original st9 backward compati- bility mode and st9+ interrupt management mode. st9 backward compatibility mode (encsr = 0) if encsr is reset, the cpu works in original st9 compatibility mode. for the duration of the inter- rupt service routine, isr is used instead of csr, and the interrupt stack frame is identical to that of the original st9: only the pc and flags are pushed. this avoids saving the csr on the stack in the event of an interrupt, thus ensuring a faster inter- rupt response time. it is not possible for an interrupt service routine to perform inter-segment calls or jumps: these in- structions would update the csr, which, in this case, is not used (isr is used instead). the code segment size for all interrupt service routines is thus limited to 64k bytes. st9+ mode (encsr = 1) if encsr is set, isr is only used to point to the in- terrupt vector table and to initialize the csr at the beginning of the interrupt service routine: the old csr is pushed onto the stack together with the pc and flags, and csr is then loaded with the con- tents of isr. in this case, iret will also restore csr from the stack. this approach allows interrupt service rou- tines to access the entire 4 mbytes of address space. the drawback is that the interrupt response time is slightly increased, because of the need to also save csr on the stack. full compatibility with the original st9 is lost in this case, because the interrupt stack frame is differ- ent. 3.3 interrupt priority levels the st9 supports a fully programmable interrupt priority structure. nine priority levels are available to define the channel priority relationships: C the on-chip peripheral channels and the eight external interrupt sources can be programmed within eight priority levels. each channel has a 3- bit field, prl (priority level), that defines its pri- ority level in the range from 0 (highest priority) to 7 (lowest priority). C the 9th level (top level priority) is reserved for the timer/watchdog or the external pseudo non-maskable interrupt. an interrupt service routine at this level cannot be interrupted in any arbitration mode. its mask can be both maskable (tli) or non-maskable (tlnm). 3.4 priority level arbitration the 3 bits of cpl (current priority level) in the central interrupt control register contain the pri- ority of the currently running program (cpu priori- ty). cpl is set to 7 (lowest priority) upon reset and can be modified during program execution either by software or automatically by hardware accord- ing to the selected arbitration mode. during every instruction, an arbitration phase takes place, during which, for every channel capa- ble of generating an interrupt, each priority level is compared to all the other requests (interrupts or dma). if the highest priority request is an interrupt, its prl value must be strictly lower (that is, higher pri- ority) than the cpl value stored in the cicr regis- ter (r230) in order to be acknowledged. the top level interrupt overrides every other priority. 3.4.1 priority level 7 (lowest) interrupt requests at prl level 7 cannot be ac- knowledged, as this prl value (the lowest possi- ble priority) cannot be strictly lower than the cpl value. this can be of use in a fully polled interrupt environment. 3.4.2 maximum depth of nesting no more than 8 routines can be nested. if an inter- rupt routine at level n is being serviced, no other interrupts located at level n can interrupt it. this guarantees a maximum number of 8 nested levels including the top level interrupt request. 3.4.3 simultaneous interrupts if two or more requests occur at the same time and at the same priority level, an on-chip daisy chain, specific to every st9 version, selects the channel encsr bit 0 1 mode st9 compatible st9+ pushed/popped registers pc, flagr pc, flagr, csr max. code size for interrupt service routine 64kb within 1 segment no limit across segments
46/268 interrupts with the highest position in the chain, as shown in figure 10 table 10. daisy chain priority 3.4.4 dynamic priority level modification the main program and routines can be specifically prioritized. since the cpl is represented by 3 bits in a read/write register, it is possible to modify dy- namically the current priority value during program execution. this means that a critical section can have a higher priority with respect to other inter- rupt requests. furthermore it is possible to priori- tize even the main program execution by modify- ing the cpl during its execution. see figure 18 figure 18. example of dynamic priority level modification in nested mode 3.5 arbitration modes the st9 provides two interrupt arbitration modes: concurrent mode and nested mode. concurrent mode is the standard interrupt arbitration mode. nested mode improves the effective interrupt re- sponse time when service routine nesting is re- quired, depending on the request priority levels. the iam control bit in the cicr register selects concurrent arbitration mode or nested arbitration mode. 3.5.1 concurrent mode this mode is selected when the iam bit is cleared (reset condition). the arbitration phase, performed during every instruction, selects the request with the highest priority level. the cpl value is not modified in this mode. start of interrupt routine the interrupt cycle performs the following steps: C all maskable interrupt requests are disabled by clearing cicr.ien. C the pc low byte is pushed onto system stack. C the pc high byte is pushed onto system stack. C if encsr is set, csr is pushed onto system stack. C the flag register is pushed onto system stack. C the pc is loaded with the 16-bit vector stored in the vector table, pointed to by the ivr. C if encsr is set, csr is loaded with isr con- tents; otherwise isr is used in place of csr until iret instruction. end of interrupt routine the interrupt service routine must be ended with the iret instruction. the iret instruction exe- cutes the following operations: C the flag register is popped from system stack. C if encsr is set, csr is popped from system stack. C the pc high byte is popped from system stack. C the pc low byte is popped from system stack. C all unmasked interrupts are enabled by setting the cicr.ien bit. C if encsr is reset, csr is used instead of isr. normal program execution thus resumes at the in- terrupted instruction. all pending interrupts remain pending until the next ei instruction (even if it is executed during the interrupt service routine). note : in concurrent mode, the source priority level is only useful during the arbitration phase, where it is compared with all other priority levels and with the cpl. no trace is kept of its value during the isr. if other requests are issued during the inter- rupt service routine, once the global cicr.ien is re-enabled, they will be acknowledged regardless of the interrupt service routines priority. this may cause undesirable interrupt response sequences. highest position lowest position inta0 inta1 intb0 intb1 intc0 intc1 intd0 intd1 sci mft int0/wdt int1/stim int2/spi int3/i2c int4/osd int5/adc int6/ds0, ds1 int7/ir 6 5 4 7 priority level main cpl is set to 5 cpl=7 main int 6 cpl=6 int6 ei cpl is set to 7 cpl6 > cpl5: int6 pending interrupt 6 has priority level 6 by main program
47/268 interrupts arbitration modes (contd) examples in the following two examples, three interrupt re- quests with different priority levels (2, 3 & 4) occur simultaneously during the interrupt 5 service rou- tine. example 1 in the first example, (simplest case, figure 19 ) the ei instruction is not used within the interrupt serv- ice routines. this means that no new interrupt can be serviced in the middle of the current one. the interrupt routines will thus be serviced one after another, in the order of their priority, until the main program eventually resumes. figure 19. simple example of a sequence of interrupt requests with: - concurrent mode selected and - ien unchanged by the interrupt routines 6 5 4 3 2 1 0 7 priority level of main int 5 int 2 int 3 int 4 main int 5 int 4 int 3 int 2 cpl is set to 7 cpl = 7 cpl = 7 cpl = 7 cpl = 7 cpl = 7 ei interrupt 2 has priority level 2 interrupt 3 has priority level 3 interrupt 4 has priority level 4 interrupt 5 has priority level 5 interrupt request
48/268 interrupts arbitration modes (contd) example 2 in the second example, (more complex, figure 20 ), each interrupt service routine sets interrupt enable with the ei instruction at the beginning of the routine. placed here, it minimizes response time for requests with a higher priority than the one being serviced. the level 2 interrupt routine (with the highest prior- ity) will be acknowledged first, then, when the ei instruction is executed, it will be interrupted by the level 3 interrupt routine, which itself will be inter- rupted by the level 4 interrupt routine. when the level 4 interrupt routine is completed, the level 3 in- terrupt routine resumes and finally the level 2 inter- rupt routine. this results in the three interrupt serv- ice routines being executed in the opposite order of their priority. it is therefore recommended to avoid inserting the ei instruction in the interrupt service rou- tine in concurrent mode . use the ei instruc- tion only in nested mode. warning: if, in concurrent mode, interrupts are nested (by executing ei in an interrupt service routine), make sure that either encsr is set or csr=isr, otherwise the iret of the innermost in- terrupt will make the cpu use csr instead of isr before the outermost interrupt service routine is terminated, thus making the outermost routine fail. figure 20. complex example of a sequence of interrupt requests with: - concurrent mode selected - ien set to 1 during interrupt service routine execution 6 5 4 3 2 1 0 7 main int 5 int 2 int 3 int 4 int 5 int 4 int 3 int 2 cpl is set to 7 cpl = 7 cpl = 7 cpl = 7 cpl = 7 cpl = 7 ei interrupt 2 has priority level 2 interrupt 3 has priority level 3 interrupt 4 has priority level 4 interrupt 5 has priority level 5 int 2 int 3 cpl = 7 cpl = 7 int 5 cpl = 7 main ei ei ei priority level of interrupt request ei
49/268 interrupts arbitration modes (contd) 3.5.2 nested mode the difference between nested mode and con- current mode, lies in the modification of the cur- rent priority level (cpl) during interrupt process- ing. the arbitration phase is basically identical to con- current mode, however, once the request is ac- knowledged, the cpl is saved in the nested inter- rupt control register (nicr) by setting the nicr bit corresponding to the cpl value (i.e. if the cpl is 3, the bit 3 will be set). the cpl is then loaded with the priority of the re- quest just acknowledged; the next arbitration cycle is thus performed with reference to the priority of the interrupt service routine currently being exe- cuted. start of interrupt routine the interrupt cycle performs the following steps: C all maskable interrupt requests are disabled by clearing cicr.ien. C cpl is saved in the special nicr stack to hold the priority level of the suspended routine. C priority level of the acknowledged routine is stored in cpl, so that the next request priority will be compared with the one of the routine cur- rently being serviced. C the pc low byte is pushed onto system stack. C the pc high byte is pushed onto system stack. C if encsr is set, csr is pushed onto system stack. C the flag register is pushed onto system stack. C the pc is loaded with the 16-bit vector stored in the vector table, pointed to by the ivr. C if encsr is set, csr is loaded with isr con- tents; otherwise isr is used in place of csr until iret instruction. figure 21. simple example of a sequence of interrupt requests with: - nested mode - ien unchanged by the interrupt routines 6 5 4 3 2 1 0 7 main int 2 int0 int4 int3 int2 cpl is set to 7 cpl=2 cpl=7 ei interrupt 2 has priority level 2 interrupt 3 has priority level 3 interrupt 4 has priority level 4 interrupt 5 has priority level 5 main int 3 cpl=3 int 6 cpl=6 int5 int 0 cpl=0 int6 int2 interrupt 6 has priority level 6 interrupt 0 has priority level 0 cpl6 > cpl3: int6 pending cpl2 < cpl4: serviced next int 2 cpl=2 int 4 cpl=4 int 5 cpl=5 priority level of interrupt request
50/268 interrupts arbitration modes (contd) end of interrupt routine the iret interrupt return instruction executes the following steps: C the flag register is popped from system stack. C if encsr is set, csr is popped from system stack. C the pc high byte is popped from system stack. C the pc low byte is popped from system stack. C all unmasked interrupts are enabled by setting the cicr.ien bit. C the priority level of the interrupted routine is popped from the special register (nicr) and copied into cpl. C if encsr is reset, csr is used instead of isr, unless the program returns to another nested routine. the suspended routine thus resumes at the inter- rupted instruction. figure 21 contains a simple example, showing that if the ei instruction is not used in the interrupt service routines, nested and concurrent modes are equivalent. figure 22 contains a more complex example showing how nested mode allows nested interrupt processing (enabled inside the interrupt service routinesi using the ei instruction) according to their priority level. figure 22. complex example of a sequence of interrupt requests with: - nested mode - ien set to 1 during the interrupt routine execution int 2 int 3 cpl=3 int 0 cpl=0 int6 6 5 4 3 2 1 0 7 main int 5 int 4 int0 int4 int3 int2 cpl is set to 7 cpl=5 cpl=4 cpl=2 cpl=7 ei interrupt 2 has priority level 2 interrupt 3 has priority level 3 interrupt 4 has priority level 4 interrupt 5 has priority level 5 int 2 int 4 cpl=2 cpl=4 int 5 cpl=5 main ei ei int 2 cpl=2 int 6 cpl=6 int5 int2 ei interrupt 6 has priority level 6 interrupt 0 has priority level 0 cpl6 > cpl3: int6 pending cpl2 < cpl4: serviced just after ei priority level of interrupt request ei
51/268 interrupts 3.6 external interrupts the standard st9 core contains 8 external inter- rupts sources grouped into four pairs. table 11. external interrupt channel grouping each source has a trigger control bit tea0,..ted1 (r242,eitr.0,..,7 page 0) to select triggering on the rising or falling edge of the external pin. if the trigger control bit is set to 1, the corresponding pending bit ipa0,..,ipd1 (r243,eipr.0,..,7 page 0) is set on the input pin rising edge, if it is cleared, the pending bit is set on the falling edge of the in- put pin. each source can be individually masked through the corresponding control bit ima0,..,imd1 (eimr.7,..,0). see figure 1 . the priority level of the external interrupt sources can be programmed among the eight priority lev- els with the control register eiplr (r245). the pri- ority level of each pair is software defined using the bits prl2, prl1. for each pair, the even channel (a0,b0,c0,d0) of the group has the even priority level and the odd channel (a1,b1,c1,d1) has the odd (lower) priority level. figure 23. priority level examples n figure 23 shows an example of priority levels. figure 1 gives an overview of the external inter- rupt control bits and vectors. C the source of the interrupt channel a1 can be selected between the external pin int4 (when ints = 1) or the on-chip standard timer. C the source of the interrupt channel b0 can be selected between the external pin int2 (when (spen,bms)=(0,0)) or the on-chip spi peripher- al. C the source of the interrupt channel intb1 can be selected between the int3 external pin (clear=1) or the i2c interrupt (clear=0) by programming the clear bit in the i2cctr reg- ister. C the source of the interrupt channel intc0 can be selected between the int4 external pin (di- on=osde=0) or the display controller interrupt (all other cases) by programming the dion, osde bits in the osder register. C the source of the interrupt channel c1 can be selected between the external pin int5 (when the ad_int bit in the ad-int register=0) or the on-chip adc (when ad-int=1). C the source of the interrupt channel d0 can be selected between the external pin int6 (when the ccid bit in the ds0cr2 or ds1cr2 regis- ter=1) or the on-chip data slicers (when ccid=0). C the source of the interrupt channel d1 can be selected between the external pin int7 (when the irwdis bit in the irsc register = 1) or the on-chip ir (when irwdis=0). warning: when using channels shared by both external interrupts and peripherals, special care must be taken to configure their control registers for both peripherals and interrupts. table 12. multiplexed interrupt sources external interrupt channel int7 int6 intd1 intd0 int5 int4 intc1 intc0 int3 int2 intb1 intb0 int1 int0 inta1 inta0 1001001 pl2d pl1d pl2c pl1c pl2b pl1b pl2a pl1a int.d1: int.c1: 001=1 int.d0: source priority priorit y source int.a0: 010=2 int.a1: 011=3 int.b1: 101=5 int.b0: 100=4 int.c0: 000=0 eiplr vr000151 0 100=4 101=5 channel internal interrupt source external interrupt source related pin inta0 timer/watch- dog int0 p3.2 inta1 stim timer int1 p3.4 intb0 spi interrupt int2 p2.4 intb1 i2c int3 p2.2 intc0 osd int4 p2.3 intc1 adc int5 p2.7 intd0 ds0 & ds1 int6 p2.1 intd1 ir int7 p2.0
52/268 interrupts external interrupts (contd) figure 1. external interrupts control bits and vectors n int a0 request vector priority level mask bit pending bit ima0 ipa0 v7 v6 v5 v4 0 0 0 0 0 1 ia0s watchdog/timer end of count int 0 pin int a1 request int b0 request int 2 pin int b1 request int c0 request int c1 request int 5 pin int d0 request ted0 int 6 pin int d1 request ted1 int 7 pin vector priority level mask bit pending bit ima1 ipa1 v7 v6 v5 v4 0 0 1 0 1 v7 v6 v5 v4 0 1 00 v7 v6 v5 v4 0 1 1 0 v7 v6 v5 v4 1 0 0 0 v7 v6 v5 v4 1 0 1 0 v7 v6 v5 v4 1 1 0 0 v7 v6 v5 v4 1 1 1 0 vector priority level vector priority level vector priority level vector priority level vector priority level vector priority level mask bit imb0 pending bit ipb0 pending bit ipb1 pending bit ipc0 pending bit ipc1 pending bit ipd0 pending bit ipd1 mask bit imb1 mask bit imc0 mask bit imc1 mask bit imd0 mask bit imd1 * shared channels, see warning * * spen,bms spi interrupt ints stim timer 0 1 ccid1 and ccid2 data slicers 0 1 tea0 teb0 * 0,0 pl2a pl1a 1 pl2c pl1c 0 pl2b pl1b 0 pl2a pl1a 1 pl2b pl1b 0 pl2c pl1c 0 pl2d pl1d 1 pl2d pl1d tea1 i2c interrupt osd display 1 0 ad-int adc * 0 1 irdwis ir * tec1 teb1 tec0 * int 1 pin int 3 pin int 4 pin or mouse dion, odse * 0,0 clear 0 1 * ccirq1 & ccid1 or ccirq2 & ccid2
53/268 interrupts 3.7 top level interrupt the top level interrupt channel can be assigned either to the external pin nmi or to the timer/ watchdog according to the status of the control bit eivr.tlis (r246.2, page 0). if this bit is high (the reset condition) the source is the external pin nmi. if it is low, the source is the timer/ watchdog end of count. when the source is the nmi external pin, the control bit eivr.tltev (r246.3; page 0) selects between the rising (if set) or falling (if reset) edge generating the interrupt request. when the selected event occurs, the cicr.tlip bit (r230.6) is set. depending on the mask situation, a top level interrupt request may be generated. two kinds of masks are available, a maskable mask and a non-maskable mask. the first mask is the cicr.tli bit (r230.5): it can be set or cleared to enable or disable respectively the top level inter- rupt request. if it is enabled, the global enable in- terrupt bit, cicr.ien (r230.4) must also be ena- bled in order to allow a top level request. the second mask nicr.tlnm (r247.7) is a set- only mask. once set, it enables the top level in- terrupt request independently of the value of cicr.ien and it cannot be cleared by the pro- gram. only the processor reset cycle can clear this bit. this does not prevent the user from ignor- ing some sources due to a change in tlis. the top level interrupt service routine cannot be interrupted by any other interrupt or dma request, in any arbitration mode, not even by a subsequent top level interrupt request. warning . the interrupt machine cycle of the top level interrupt does not clear the cicr.ien bit, and the corresponding iret does not set it. fur- thermore the tli never modifies the cpl bits and the nicr register. 3.8 on-chip peripheral interrupts the general structure of the peripheral interrupt unit is described here, however each on-chip pe- ripheral has its own specific interrupt unit contain- ing one or more interrupt channels, or dma chan- nels. please refer to the specific peripheral chap- ter for the description of its interrupt features and control registers. the on-chip peripheral interrupt channels provide the following control bits: C interrupt pending bit (ip). set by hardware when the trigger event occurs. can be set/ cleared by software to generate/cancel pending interrupts and give the status for interrupt polling. C interrupt mask bit (im). if im = 0, no interrupt request is generated. if im =1 an interrupt re- quest is generated whenever ip = 1 and cicr.ien = 1. C priority level (prl, 3 bits). these bits define the current priority level, prl=0: the highest pri- ority, prl=7: the lowest priority (the interrupt cannot be acknowledged) C interrupt vector register (ivr, up to 7 bits). the ivr points to the vector table which itself contains the interrupt routine start address. figure 24. top level interrupt structure n n watchdog enable wden watchdog timer end of count nmi or tltev mux tlis tlip tlnm tli ien pending mask top level interrupt va00294 core reset request
54/268 interrupts 3.9 interrupt response time the interrupt arbitration protocol functions com- pletely asynchronously from instruction flow and requires 5 clock cycles. one more cpuclk cycle is required when an interrupt is acknowledged. requests are sampled every 5 cpuclk cycles. if the interrupt request comes from an external pin, the trigger event must occur a minimum of one intclk cycle before the sampling time. when an arbitration results in an interrupt request being generated, the interrupt logic checks if the current instruction (which could be at any stage of execution) can be safely aborted; if this is the case, instruction execution is terminated immedi- ately and the interrupt request is serviced; if not, the cpu waits until the current instruction is termi- nated and then services the request. instruction execution can normally be aborted provided no write operation has been performed. for an interrupt deriving from an external interrupt channel, the response time between a user event and the start of the interrupt service routine can range from a minimum of 26 clock cycles to a max- imum of 55 clock cycles (div instruction), 53 clock cycles (divws and mul instructions) or 49 for other instructions. for a non-maskable top level interrupt, the re- sponse time between a user event and the start of the interrupt service routine can range from a min- imum of 22 clock cycles to a maximum of 51 clock cycles (div instruction), 49 clock cycles (divws and mul instructions) or 45 for other instructions. in order to guarantee edge detection, input signals must be kept low/high for a minimum of one intclk cycle. an interrupt machine cycle requires a basic 18 in- ternal clock cycles (cpuclk), to which must be added a further 2 clock cycles if the stack is in the register file. 2 more clock cycles must further be added if the csr is pushed (encsr =1). the interrupt machine cycle duration forms part of the two examples of interrupt response time previ- ously quoted; it includes the time required to push values on the stack, as well as interrupt vector handling. in wait for interrupt mode, a further cycle is re- quired as wake-up delay.
55/268 interrupts 3.10 interrupt registers central interrupt control register (cicr) r230 - read/write register group: system reset value: 1000 0111 (87h) bit 7 = gcen : global counter enable. this bit enables the 16-bit multifunction timer pe- ripheral. 0: mft disabled 1: mft enabled bit 6 = tlip : top level interrupt pending . this bit is set by hardware when top level inter- rupt (tli) trigger event occurs. it is cleared by hardware when a tli is acknowledged. it can also be set by software to implement a software tli. 0: no tli pending 1: tli pending bit 5 = tli : top level interrupt. this bit is set and cleared by software. 0: a top level interrupt is generared when tlip is set, only if tlnm=1 in the nicr register (inde- pendently of the value of the ien bit). 1: a top level interrupt request is generated when ien=1 and the tlip bit are set. bit 4 = ien : interrupt enable . this bit is cleared by the interrupt machine cycle (except for a tli). it is set by the iret instruction (except for a return from tli). it is set by the ei instruction. it is cleared by the di instruction. 0: maskable interrupts disabled 1: maskable interrupts enabled note: the ien bit can also be changed by soft- ware using any instruction that operates on regis- ter cicr, however in this case, take care to avoid spurious interrupts, since ien cannot be cleared in the middle of an interrupt arbitration. only modify the ien bit when interrupts are disabled or when no peripheral can generate interrupts. for exam- ple, if the state of ien is not known in advance, and its value must be restored from a previous push of cicr on the stack, use the sequence di; pop cicr to make sure that no interrupts are be- ing arbitrated when cicr is modified. bit 3 = iam : interrupt arbitration mode . this bit is set and cleared by software. 0: concurrent mode 1: nested mode bit 2:0 = cpl[2:0]: current priority level . these bits define the current priority level. cpl=0 is the highest priority. cpl=7 is the lowest priority. these bits may be modified directly by the interrupt hardware when nested interrupt mode is used. 70 gcen tlip tli ien iam cpl2 cpl1 cpl0
56/268 interrupts interrupt registers (contd) external interrupt trigger register (eitr) r242 - read/write register page: 0 reset value: 0000 0000 (00h) bit 7 = ted1 : intd1 trigger event bit 6 = ted0 : intd0 trigger event bit 5 = tec1 : intc1 trigger event bit 4 = tec0 : intc0 trigger event bit 3 = teb1 : intb1 trigger event bit 2 = teb0 : intb0 trigger event bit 1 = tea1 : inta1 trigger event bit 0 = tea0 : inta0 trigger event these bits are set and cleared by software. 0: select falling edge as interrupt trigger event 1: select rising edge as interrupt trigger event external interrupt pending register (eipr) r243 - read/write register page: 0 reset value: 0000 0000 (00h) bit 7 = ipd1 : intd1 interrupt pending bit bit 6 = ipd0 : intd0 interrupt pending bit bit 5 = ipc1 : intc1 interrupt pending bit bit 4 = ipc0 : intc0 interrupt pending bit bit 3 = ipb1 : intb1 interrupt pending bit bit 2 = ipb0 : intb0 interrupt pending bit bit 1 = ipa1 : inta1 interrupt pending bit bit 0 = ipa0 : inta0 interrupt pending bit these bits are set by hardware on occurrence of a trigger event (as specified in the eitr register) and are cleared by hardware on interrupt acknowl- edge. they can also be set by software to imple- ment a software interrupt. 0: no interrupt pending 1: interrupt pending external interrupt mask-bit register (eimr) r244 - read/write register page: 0 reset value: 0000 0000 (00h ) bit 7 = imd1 : intd1 interrupt mask bit 6 = imd0 : intd0 interrupt mask bit 5 = imc1 : intc1 interrupt mask bit 4 = imc0 : intc0 interrupt mask bit 3 = imb1 : intb1 interrupt mask bit 2 = imb0 : intb0 interrupt mask bit 1 = ima1 : inta1 interrupt mask bit 0 = ima0 : inta0 interrupt mask these bits are set and cleared by software. 0: interrupt masked 1: interrupt not masked (an interrupt is generated if the ipxx and ien bits = 1) 70 ted1 ted0 tec1 tec0 teb1 teb0 tea1 tea0 70 ipd1 ipd0 ipc1 ipc0 ipb1 ipb0 ipa1 ipa0 70 imd1 imd0 imc1 imc0 imb1 imb0 ima1 ima0
57/268 interrupts interrupt registers (contd) external interrupt priority level register (eiplr) r245 - read/write register page: 0 reset value: 1111 1111 (ffh ) bit 7:6 = pl2d, pl1d: intd0, d1 priority level. bit 5:4 = pl2c, pl1c : intc0, c1 priority level. bit 3:2 = pl2b, pl1b : intb0, b1 priority level. bit 1:0 = pl2a, pl1a : inta0, a1 priority level. these bits are set and cleared by software. the priority is a three-bit value. the lsb is fixed by hardware at 0 for channels a0, b0, c0 and d0 and at 1 for channels a1, b1, c1 and d1. external interrupt vector register (eivr ) r246 - read/write register page: 0 reset value: xxxx 0110b (x6h) bit 7:4 = v[7:4] : most significant nibble of external interrupt vector . these bits are not initialized by reset. for a repre- sentation of how the full vector is generated from v[7:4] and the selected external interrupt channel, refer to figure 1 . bit 3 = tltev : top level trigger event bit. this bit is set and cleared by software. 0: select falling edge as nmi trigger event 1: select rising edge as nmi trigger event bit 2 = tlis : top level input selection . this bit is set and cleared by software. 0: watchdog end of count is tl interrupt source 1: nmi is tl interrupt source bit 1 = ia0s : interrupt channel a0 selection. this bit is set and cleared by software. 0: watchdog end of count is inta0 source 1: external interrupt pin is inta0 source bit 0 = ewen : external wait enable. this bit is set and cleared by software. 0: waitn pin disabled 1: waitn pin enabled (to stretch the external memory access cycle). note: for more details on wait mode refer to the section describing the waitn pin in the external memory chapter. nested interrupt control (nicr) r247 - read/write register page: 0 reset value: 0000 0000 (00h) bit 7 = tlnm : top level not maskable . this bit is set by software and cleared only by a hardware reset. 0: top level interrupt maskable. a top level re- quest is generated if the ien, tli and tlip bits =1 1: top level interrupt not maskable. a top level request is generated if the tlip bit =1 bit 6:0 = hl[6:0] : hold level x these bits are set by hardware when, in nested mode, an interrupt service routine at level x is in- terrupted from a request with higher priority (other than the top level interrupt request). they are cleared by hardware at the iret execution when the routine at level x is recovered. 70 pl2d pl1d pl2c pl1c pl2b pl1b pl2a pl1a pl2x pl1x hardware bit priority 00 0 1 0 (highest) 1 01 0 1 2 3 10 0 1 4 5 11 0 1 6 7 (lowest) 70 v7 v6 v5 v4 tltev tlis iaos ewen 70 tlnm hl6 hl5 hl4 hl3 hl2 hl1 hl0
58/268 interrupts interrupt registers (contd) external memory register 2 (emr2) r246 - read/write register page: 21 reset value: 0000 1111 (0fh) bit 7, 5:0 = reserved, keep in reset state. refer to the external memory interface chapter. bit 6 = encsr : enable code segment register. this bit is set and cleared by software. it affects the st9 cpu behaviour whenever an interrupt re- quest is issued. 0: the cpu works in original st9 compatibility mode. for the duration of the interrupt service routine, isr is used instead of csr, and the in- terrupt stack frame is identical to that of the orig- inal st9: only the pc and flags are pushed. this avoids saving the csr on the stack in the event of an interrupt, thus ensuring a faster in- terrupt response time. the drawback is that it is not possible for an interrupt service routine to perform inter-segment calls or jumps: these in- structions would update the csr, which, in this case, is not used (isr is used instead). the code segment size for all interrupt service rou- tines is thus limited to 64k bytes. 1: isr is only used to point to the interrupt vector table and to initialize the csr at the beginning of the interrupt service routine: the old csr is pushed onto the stack together with the pc and flags, and csr is then loaded with the contents of isr. in this case, iret will also restore csr from the stack. this approach allows interrupt service routines to access the entire 4 mbytes of address space; the drawback is that the inter- rupt response time is slightly increased, be- cause of the need to also save csr on the stack. full compatibility with the original st9 is lost in this case, because the interrupt stack frame is different; this difference, however, should not affect the vast majority of programs. 70 0encsr001111
59/268 on-chip direct memory access (dma) 4 on-chip direct memory access (dma) 4.1 introduction the st9 includes on-chip direct memory access (dma) in order to provide high-speed data transfer between peripherals and memory or register file. multi-channel dma is fully supported by peripher- als having their own controller and dma chan- nel(s). each dma channel transfers data to or from contiguous locations in the register file, or in memory. the maximum number of bytes that can be transferred per transaction by each dma chan- nel is 222 with the register file, or 65536 with memory. the dma controller in the peripheral uses an indi- rect addressing mechanism to dma pointers and counter registers stored in the register file. this is the reason why the maximum number of trans- actions for the register file is 222, since two reg- isters are allocated for the pointer and counter. register pairs are used for memory pointers and counters in order to offer the full 65536 byte and count capability. 4.2 dma priority levels the 8 priority levels used for interrupts are also used to prioritize the dma requests, which are ar- bitrated in the same arbitration phase as interrupt requests. if the event occurrence requires a dma transaction, this will take place at the end of the current instruction execution. when an interrupt and a dma request occur simultaneously, on the same priority level, the dma request is serviced before the interrupt. an interrupt priority request must be strictly higher than the cpl value in order to be acknowledged, whereas, for a dma transaction request, it must be equal to or higher than the cpl value in order to be executed. thus only dma transaction requests can be acknowledged when the cpl=0. dma requests do not modify the cpl value, since the dma transaction is not interruptable. figure 25. dma data transfer peripheral vr001834 data address counter transferred register file or memory register file register file start address counter value 0 df data group f peripheral paged registers
60/268 on-chip direct memory access (dma) 4.3 dma transactions the purpose of an on-chip dma channel is to transfer a block of data between a peripheral and the register file, or memory. each dma transfer consists of three operations: C a load from/to the peripheral data register to/ from a location of register file (or memory) ad- dressed through the dma address register (or register pair) C a post-increment of the dma address register (or register pair) C a post-decrement of the dma transaction coun- ter, which contains the number of transactions that have still to be performed. if the dma transaction is carried out between the peripheral and the register file ( figure 26 ), one register is required to hold the dma address, and one to hold the dma transaction counter. these two registers must be located in the register file: the dma address register in the even address register, and the dma transaction counter in the next register (odd address). they are pointed to by the dma transaction counter pointer register (dcpr), located in the peripherals paged regis- ters. in order to select a dma transaction with the register file, the control bit dcpr.rm (bit 0 of dcpr) must be set. if the transaction is made between the peripheral and memory , a register pair (16 bits) is required for the dma address and the dma transaction counter ( figure 27 ). thus, two register pairs must be located in the register file. the dma transaction counter is pointed to by the dma transaction counter pointer register (dcpr), the dma address is pointed to by the dma address pointer register (dapr),both dcpr and dapr are located in the paged regis- ters of the peripheral. figure 26. dma between register file and peripheral idcr ivr dapr dcpr data paged registers registers system dma counter dma address ffh f0h e0h dfh efh memory 000000h data already transferred end of block interrupt service routine dma table dma transaction isr address 000100h vector table register file peripheral paged registers
61/268 on-chip direct memory access (dma) dma transactions (contd) when selecting the dma transaction with memory, bit dcpr.rm (bit 0 of dcpr) must be cleared. to select between using the isr or the dmasr reg- ister to extend the address, (see memory manage- ment unit chapter), the control bit dapr.ps (bit 0 of dapr) must be cleared or set respectively. the dma transaction counter must be initialized with the number of transactions to perform and will be decremented after each transaction. the dma address must be initialized with the starting ad- dress of the dma table and is increased after each transaction. these two registers must be located between addresses 00h and dfh of the register file. once a dma channel is initialized, a transfer can start. the direction of the transfer is automatically defined by the type of peripheral and programming mode. once the dma table is completed (the transaction counter reaches 0 value), an interrupt request to the cpu is generated. when the interrupt pending (idcr.ip) bit is set by a hardware event (or by software), and the dma mask bit (idcr.dm) is set, a dma request is gen- erated. if the priority level of the dma source is higher than, or equal to, the current priority level (cpl), the dma transfer is executed at the end of the current instruction. dma transfers read/write data from/to the location pointed to by the dma address register, the dma address register is in- cremented and the transaction counter register is decremented. when the contents of the trans- action counter are decremented to zero, the dma mask bit (dm) is cleared and an interrupt request is generated, according to the interrupt mask bit (end of block interrupt). this end-of-block inter- rupt request is taken into account, depending on the prl value. warning . dma requests are not acknowledged if the top level interrupt service is in progress. figure 27. dma between memory and peripheral n idcr ivr dapr dcpr data paged registers registers system dma transaction counter dma address ffh f0h e0h dfh efh memory 000000h data already transferred end of block interrupt service routine dma table dma transaction isr address 000100h vector table register file peripheral paged registers
62/268 on-chip direct memory access (dma) dma transactions (contd) 4.4 dma cycle time the interrupt and dma arbitration protocol func- tions completely asynchronously from instruction flow. requests are sampled every 5 cpuclk cycles. dma transactions are executed if their priority al- lows it. a dma transfer with the register file requires 8 cpuclk cycles. a dma transfer with memory requires 16 cpuclk cycles, plus any required wait states. 4.5 swap mode an extra feature which may be found on the dma channels of some peripherals (e.g. the multifunc- tion timer) is the swap mode. this feature allows transfer from two dma tables alternatively. all the dma descriptors in the register file are thus dou- bled. two dma transaction counters and two dma address pointers allow the definition of two fully in- dependent tables (they only have to belong to the same space, register file or memory). the dma transaction is programmed to start on one of the two tables (say table 0) and, at the end of the block, the dma controller automatically swaps to the other table (table 1) by pointing to the other dma descriptors. in this case, the dma mask (dm bit) control bit is not cleared, but the end of block interrupt request is generated to allow the optional updating of the first data table (table 0). until the swap mode is disabled, the dma control- ler will continue to swap between dma table 0 and dma table 1. n
63/268 on-chip direct memory access (dma) 4.6 dma registers as each peripheral dma channel has its own spe- cific control registers, the following register list should be considered as a general example. the names and register bit allocations shown here may be different from those found in the peripheral chapters. dma counter pointer register (dcpr) read/write address set by peripheral reset value: undefined bit 7:1 = c[7:1] : dma transaction counter point- er. software should write the pointer to the dma transaction counter in these bits. bit 0 = rm : register file/memory selector. this bit is set and cleared by software. 0: dma transactions are with memory (see also dapr.dp) 1: dma transactions are with the register file generic external peripheral inter- rupt and dma control (idcr) read/write address set by peripheral reset value: undefined bit 5 = ip : interrupt pending . this bit is set by hardware when the trigger event occurs. it is cleared by hardware when the request is acknowledged. it can be set/cleared by software in order to generate/cancel a pending request. 0: no interrupt pending 1: interrupt pending bit 4 = dm : dma request mask . this bit is set and cleared by software. it is also cleared when the transaction counter reaches zero (unless swap mode is active). 0: no dma request is generated when ip is set. 1: dma request is generated when ip is set bit 3 = im : end of block interrupt mask . this bit is set and cleared by software. 0: no end of block interrupt request is generated when ip is set 1: end of block interrupt is generated when ip is set. dma requests depend on the dm bit value as shown in the table below. bit 2:0 = prl[2:0] : source priority level . these bits are set and cleared by software. refer to section 4.2 for a description of priority levels. dma address pointer register (dapr) read/write address set by peripheral reset value: undefined bit 7:1 = a[7:1] : dma address register(s) pointer software should write the pointer to the dma ad- dress register(s) in these bits. bit 0 = ps : memory segment pointer selector : this bit is set and cleared by software. it is only meaningful if dcpr.rm=0. 0: the isr register is used to extend the address of data transferred by dma (see mmu chapter). 1: the dmasr register is used to extend the ad- dress of data transferred by dma (see mmu chapter). 70 c7 c6 c5 c4 c3 c2 c1 rm 70 ip dm im prl2 prl1 prl0 dm im meaning 10 a dma request generated without end of block interrupt when ip=1 11 a dma request generated with end of block in- terrupt when ip=1 00 no end of block interrupt or dma request is generated when ip=1 01 an end of block interrupt is generated without associated dma request (not used) prl2 prl1 prl0 source priority level 0000 h ighest 0011 0102 0113 1004 1015 1106 1117 lo west 70 a7 a6 a5 a4 a3 a2 a1 ps
64/268 reset and clock control unit (rccu) 5 reset and clock control unit (rccu) 5.1 introduction the reset and clock control unit (rccu) com- prises two distinct sections: C the clock control unit, which generates and manages the internal clock signals. C the reset/stop manager, which detects and flags hardware, software and watchdog gener- ated resets. 5.2 clock control registers mode register (moder) r235 - read/write system register reset value: 1110 0000 (e0h) *note : this register contains bits which relate to other functions; these are described in the chapter dealing with device architecture. only those bits relating to clock functions are described here. bit 5 = div2 : oscin divided by 2 . this bit controls the divide by 2 circuit which oper- ates on the oscin clock. 0: no division of the oscin clock 1: oscin clock is internally divided by 2 bit 4:2 = prs[2:0] : clock prescaling . these bits define the prescaler value used to pres- cale cpuclk from intclk. when these three bits are reset, the cpuclk is not prescaled, and is equal to intclk; in all other cases, the internal clock is prescaled by the value of these three bits plus one. clock control register (clkctl) r240 - read write register page: 55 reset value: 0000 0000 (00h) bit 7:4 = reserved. must be kept reset for normal operation. bit 3 = sresen : software reset enable. 0: the halt instruction turns off the quartz, the pll and the ccu 1: a reset is generated when halt is executed bit 2:0 = reserved. must be kept reset for normal operation. clock flag register (clk_flag) r242 - read/write register page: 55 reset value: 0100 1000 after a watchdog reset reset value: 0010 1000 after a software reset reset value: 0000 1000 after a power-on reset warning : if this register is accessed with a logi- cal instruction, such as and or or, some bits may not be set as expected. bit 7 = reserved. must be kept reset for normal operation. bit 6 = wdgres : watchdog reset flag. this bit is read only. 0: no watchdog reset occurred 1: watchdog reset occurred bit 5 = softres : software reset flag. this bit is read only. 0: no software reset occurred 1: software reset occurred (halt instruction) bit 4:0 = reserved. must be kept reset for normal operation. 70 - - div2 prs2 prs1 prs0 - - 70 ---- sre- sen --- 70 - wdg res soft res -----
65/268 reset and clock control unit (rccu) 5.3 oscillator characteristics because of the real time need of the application, it is assumed the st92196a will be used with a 4 mhz crystal fed to the core by the frequency mul- tiplier output after it is started and stabilized. 5.3.1 halt state when a halt instruction is processed, it stops the main crystal oscillator preventing any derived clock into the chip. exit from the halt state can be obtained through a main system reset. it should be noted that, if the watchdog function is enabled, a halt instruction will not disable the os- cillator. this to avoid stopping the watchdog if a halt code is executed in error. when this occurs, the cpu will be reset when the watchdog times out or when an external reset is applied figure 28. crystal oscillator table 13. crystal specification legend : c l1 , c l2 : maximum total capacitances on pins oscin and oscout (the value includes the external capaci- tance tied to the pin cl1 and cl2 plus the parasitic capac- itance of the board and of the device). note : the table is relative to the fundamental quartz crys- tal only (not ceramic resonator). figure 29. internal oscillator schematic oscin oscout c l1 c l2 st9 crystal clock vr02116a 1m* *recommended for oscillator stability c 1 =c 2 = 56pf c 1 =c 2 = 47pf rs max (ohm) 200 260 vr02086a halt oscin oscout r in r out r
66/268 reset and clock control unit (rccu) 5.4 reset/stop manager the reset/stop manager resets the device when one of the three following triggering events occurs: C a hardware reset, consequence of a falling edge on the reset pin. C a software reset, consequence of an halt in- struction when enabled. C a watchdog end of count. the reset input is schmitt triggered. note: the memorized internal reset (called re- seti ) will be maintained active for a duration of 32768 oscin periods (about 8 ms for a 4 mhz crys- tal) after the external input is released (set high). this reseti internal reset signal is output on the i/o port bit p5.0 (active low) during the whole reset phase until the p5.0 configuration is changed by software. the true internal reset (to all macrocells) will only be released 511 reference clock periods after the memorized internal reset is released. it is possible to know which was the last reset triggering event, by reading bits 5 and 6 of register clk_flag. figure 30. reset overview n figure 31. recommended signal to be applied on reset pin build-up counter rccu true reset reseti memorized reset internal reset v reset v dd 0.7 v dd 0.3 v dd 20 s minimum
67/268 timing and clock controller (tcc) 6 timing and clock controller (tcc) 6.1 frequency multipliers two on-chip frequency multipliers generate the proper frequencies for: the core/real time periph- erals and the display related time base. they follow the same basic scheme based on an integrated vco driven by a three state phase comparator and a charge-pump (1 pin used for off- chip filtering components; a resistor in series with a capacitor tied to ground). for both the core and the display frequency mul- tipliers, a 4 bit programmable feed-back counter allows the adjustment of the multiplying factor to the application needs (a 4 mhz crystal is as- sumed). figure 32. timing and clock controller block diagram fosd fcpu synchronised clock to osdram controller pixclk to display controller fpixc skwen skwl [3:0] 4mhz real clock to ir, sci, ds... wait for interrupt bus request memory wait state cpu clock control prescaler main clock controller div 2 (moder.5) fmsl frequency xtal osc multiplier by 2 by 2 div skdiv2 fml [3:0] fmen div by 2 div frequency multiplier prs [2:0] fmen intclk adc, spi. oscout oscin skew corrector cpuclk (core clock) clock) to timer, hsync (peripheral fosd 4mhz real clock to ir, sci, ds... div 2 (moder.5) by 2 div adc, spi.
68/268 timing and clock controller (tcc) frequency multipliers (contd) off-chip filter components (to be confirmed) C core frequency multiplier (fcpu pin) : 1.2k ohms; 47 nf plus 100 pf between the fcpu pin and gnd. C skew frequency multiplier (fosd pin) : 1.2k ohms; 47 nf plus 100 pf between the fosd pin and gnd. the frequency multipliers are off during and upon exiting from the reset phase. the user must pro- gram the desired multiplying factor, start the multi- plier and then wait for its stability (refer to the elec- trical characteristics chapter for the specified de- lay). once the core/peripherals multiplier is stabilized, the main clock controller can be re-programmed through the fmsl bit in the mccr register to pro- vide the final frequency (cpuclk) to the cpu. the frequency multipliers are automatically switched off when the microprocessor enters halt mode (the halt mode forces the control register to its reset status). table 14. examples of cpu speed choices note: 24 mhz is the max. authorized frequency. caution: the values indicated in this table are the only authorized values. table 15. pixclk frequency choices crystal frequency fml (3:0) cpuclk skdiv2=0 4 mhz 4 10 mhz 5 12 mhz 6 14 mhz 7 16 mhz 8 18 mhz 9 20 mhz 10 22 mhz 11 24 mhz crystal frequency skw (3:0) fpixc pixclk skdiv2=0 4 mhz 6 0 14 mhz 7 0 16 mhz 8 0 18 mhz 9 0 20 mhz 10 0 22 mhz 11 0 24 mhz 6 1 28 mhz 7 1 32 mhz 8 1 36 mhz 9 1 40 mhz
69/268 timing and clock controller (tcc) 6.2 register description skew clock control register (skccr) r254 - read/ write register page: 43 reset value: 0000 0000 (00h) the halt mode forces the register to its initializa- tion state. bit 7= skwen: frequency multiplier enable bit. 0: fm disabled (reset state), low-power consump- tion mode. 1: fm is enabled providing clock to the skew cor- rector. the skwen bit must be set only after programming the skw(3-0) bits. bit 6 = skdiv2: skew divide-by-2 enable bit. 0: divide-by-2 disabled. 1: divide-by-2 enabled. this bit must be kept in reset state. bit 5:4 = reserved. these bits are forced to 0 by hardware. bit 3:0 = skw: skew counter. these 4 bits program the down-counter inserted in the feedback loop of the frequency multiplier which generates the internal multiplied frequency pixclk. the pixclk value is calculated as fol- lows : if fpixc=0 : f(pixclk)=crystal frequency * [ (skw(3:0)+1) ]/2 if fpixc=1 : f(pixclk)=crystal frequency * [ (skw(3:0)+1) ] note: to program the fpixc bit, refer to the de- scription of the osder register in the osd chap- ter. main clock control register (mccr) r253 - read/ write register page: 43 reset value: 0000 0000 (00h) the halt mode forces the register to its initializa- tion state. bit 7 = fmen: frequency multiplier enable bit . 0: fm disabled (reset state), low-power consump- tion mode. 1: fm is enabled, providing clock to the cpu. the fmen bit must be set only after programming the fml(3:0) bits. bit 6= fmsl: frequency multiplier select bit. this bit controls the choice of the st9 core internal frequency between the external crystal frequency and the main clock issued by the frequency multi- plier. in order to secure the application, the st9 core in- ternal frequency is automatically switched back to the external crystal frequency if the frequency mul- tiplier is switched off (fmen =0) regardless of the value of the fmsl bit. care must be taken to reset the fmsl bit before any frequency multiplier can restart (fmen set back to 1). after reset, the external crystal frequency is al- ways sent to the st9 core. bit 5:4 = reserved. these bits are forced to 0 by hardware. bit 3:0 = fml: fm counter. these 4 bits program the down-counter inserted in the feed-back loop of the frequency multiplier which generates the internal multiplied frequency fimf. the fimf value is calculated as follows : fimf = crystal frequency * [ (fml(3:0) + 1) ] /2 7 6 5 4 3210 skwen skdiv2 0 0 skw3 skw2 skw1 skw0 7 6 5 4 3210 fmen fmsl 0 0 fml3 fml2 fml1 fml0
70/268 i/o ports 7 i/o ports 7.1 introduction st9 devices feature flexible individually program- mable multifunctional input/output lines. refer to the pin description chapter for specific pin alloca- tions. these lines, which are logically grouped as 8-bit ports, can be individually programmed to pro- vide digital input/output and analog input, or to connect input/output signals to the on-chip periph- erals as alternate pin functions. all ports can be in- dividually configured as an input, bi-directional, output or alternate function. in addition, pull-ups can be turned off for open-drain operation, and weak pull-ups can be turned on in their place, to avoid the need for off-chip resistive pull-ups. ports configured as open drain must never have voltage on the port pin exceeding v dd (refer to the electri- cal characteristics section). depending on the specific port, input buffers are software selectable to be ttl or cmos compatible, however on sch- mitt trigger ports, no selection is possible. 7.2 specific port configurations refer to the pin description chapter for a list of the specific port styles and reset values. 7.3 port control registers each port is associated with a data register (pxdr) and three control registers (pxc0, pxc1, pxc2). these define the port configuration and al- low dynamic configuration changes during pro- gram execution. port data and control registers are mapped into the register file as shown in fig- ure 33 . port data and control registers are treated just like any other general purpose register. there are no special instructions for port manipulation: any instruction that can address a register, can ad- dress the ports. data can be directly accessed in the port register, without passing through other memory or accumulator locations. figure 33. i/o register map group e group f page 2 group f page 3 group f page 43 system registers ffh reserved p7dr p9dr r255 feh p3c2 p7c2 p9c2 r254 fdh p3c1 p7c1 p9c1 r253 fch p3c0 p7c0 p9c0 r252 fbh reserved p6dr p8dr r251 fah p2c2 p6c2 p8c2 r250 f9h p2c1 p6c1 p8c1 r249 f8h p2c0 p6c0 p8c0 r248 f7h reserved reserved reserved r247 f6h p1c2 p5c2 r246 e5h p5dr r229 f5h p1c1 p5c1 r245 e4h p4dr r228 f4h p1c0 p5c0 r244 e3h p3dr r227 f3h reserved reserved r243 e2h p2dr r226 f2h p0c2 p4c2 r242 e1h p1dr r225 f1h p0c1 p4c1 r241 e0h p0dr r224 f0h p0c0 p4c0 r240
71/268 i/o ports port control registers (contd) during reset, ports with weak pull-ups are set in bidirectional/weak pull-up mode and the output data register is set to ffh. this condition is also held after reset, except for ports 0 and 1 in rom- less devices, and can be redefined under software control. bidirectional ports without weak pull-ups are set in high impedance during reset. to ensure proper levels during reset, these ports must be externally connected to either v dd or v ss through external pull-up or pull-down resistors. other reset conditions may apply in specific st9 devices. 7.4 input/output bit configuration by programming the control bits pxc0.n and pxc1.n (see figure 34 ) it is possible to configure bit px.n as input, output, bidirectional or alternate function output, where x is the number of the i/o port, and n the bit within the port (n = 0 to 7). when programmed as input, it is possible to select the input level as ttl or cmos compatible by pro- gramming the relevant pxc2.n control bit. this option is not available on schmitt trigger ports. the output buffer can be programmed as push- pull or open-drain. a weak pull-up configuration can be used to avoid external pull-ups when programmed as bidirec- tional (except where the weak pull-up option has been permanently disabled in the pin hardware as- signment). each pin of an i/o port may assume software pro- grammable alternate functions (refer to the de- vice pin description and to section 7.5). to output signals from the st9 peripherals, the port must be configured as af out. on st9 devices with a/d converter(s), configure the ports used for analog inputs as af in. the basic structure of the bit px.n of a general pur- pose port px is shown in figure 35 . independently of the chosen configuration, when the user addresses the port as the destination reg- ister of an instruction, the port is written to and the data is transferred from the internal data bus to the output master latches. when the port is ad- dressed as the source register of an instruction, the port is read and the data (stored in the input latch) is transferred to the internal data bus. when px.n is programmed as an input : (see figure 36 ). C the output buffer is forced tristate. C the data present on the i/o pin is sampled into the input latch at the beginning of each instruc- tion execution. C the data stored in the output master latch is copied into the output slave latch at the end of the execution of each instruction. thus, if bit px.n is reconfigured as an output or bidirectional, the data stored in the output slave latch will be re- flected on the i/o pin.
72/268 i/o ports input/output bit configuration (contd) figure 34. control bits n table 16. port bit configuration table (n = 0, 1... 7; x = port number) (1) for a/d converter inputs. legend: x = port n = bit af = alternate function bid = bidirectional cmos= cmos standard input levels hi-z = high impedance in = input od = open drain out = output pp = push-pull ttl = ttl standard input levels wp = weak pull-up bit 7 bit n bit 0 pxc2 pxc27 pxc2n pxc20 pxc1 pxc17 pxc1n pxc10 pxc0 pxc07 pxc0n pxc00 general purpose i/o pins a/d pins pxc2n pxc1n pxc0n 0 0 0 1 0 0 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 pxn configuration bid bid out out in in af out af out af in pxn output type wp od od pp od hi-z hi-z pp od hi-z (1) pxn input type ttl (or schmitt trigger) ttl (or schmitt trigger) ttl (or schmitt trigger) ttl (or schmitt trigger) cmos (or schmitt trigger) ttl (or schmitt trigger) ttl (or schmitt trigger) ttl (or schmitt trigger) analog input
73/268 i/o ports input/output bit configuration (contd) figure 35. basic structure of an i/o port pin figure 36. input configuration n n figure 37. output configuration n output slave latch output master latch input latch internal data bus i/o pin push-pull tristate open drain weak pull-up from peripheral output output input bidirectional alternate function to peripheral inputs and ttl / cmos (or schmitt trigger) interrupts alternate function input output bidirectional output master latch input latch output slave latch internal data bus i/o pin tristate to peripheral inputs and ttl / cmos (or schmitt trigger) interrupts output master latch input latch output slave latch internal data bus i/o pin open drain ttl (or schmitt trigger) push-pull to peripheral inputs and interrupts
74/268 i/o ports input/output bit configuration (contd) when px.n is programmed as an output : ( figure 37 ) C the output buffer is turned on in an open-drain or push-pull configuration. C the data stored in the output master latch is copied both into the input latch and into the out- put slave latch, driving the i/o pin, at the end of the execution of the instruction. when px.n is programmed as bidirectional : ( figure 38 ) C the output buffer is turned on in an open-drain or weak pull-up configuration (except when dis- abled in hardware). C the data present on the i/o pin is sampled into the input latch at the beginning of the execution of the instruction. C the data stored in the output master latch is copied into the output slave latch, driving the i/ o pin, at the end of the execution of the instruc- tion. warning : due to the fact that in bidirectional mode the external pin is read instead of the output latch, particular care must be taken with arithme- tic/logic and boolean instructions performed on a bidirectional port pin. these instructions use a read-modify-write se- quence, and the result written in the port register depends on the logical level present on the exter- nal pin. this may bring unwanted modifications to the port output register content. for example: port register content, 0fh external port value, 03h (bits 3 and 2 are externally forced to 0) a bset instruction on bit 7 will return: port register content, 83h external port value, 83h (bits 3 and 2 have been cleared). to avoid this situation, it is suggested that all oper- ations on a port, using at least one bit in bidirec- tional mode, are performed on a copy of the port register, then transferring the result with a load in- struction to the i/o port. when px.n is programmed as a digital alter- nate function output : ( figure 39 ) C the output buffer is turned on in an open-drain or push-pull configuration. C the data present on the i/o pin is sampled into the input latch at the beginning of the execution of the instruction. C the signal from an on-chip function is allowed to load the output slave latch driving the i/o pin. signal timing is under control of the alternate function. if no alternate function is connected to px.n, the i/o pin is driven to a high level when in push-pull configuration, and to a high imped- ance state when in open drain configuration. figure 38. bidirectional configuration n n figure 39. alternate function configuration n n n n n n output master latch input latch output slave latch internal data bus i/o pin weak pull-up ttl (or schmitt trigger) open drain to peripheral inputs and interrupts input latch from internal data bus i/o pin open drain ttl (or schmitt trigger) push-pull peripheral output to peripheral inputs and interrupts output slave latch
75/268 - alternate function architecture 7.5 alternate function architecture each i/o pin may be connected to three different types of internal signal: C data bus input/output C alternate function input C alternate function output 7.5.1 pin declared as i/o a pin declared as i/o, is connected to the i/o buff- er. this pin may be an input, an output, or a bidi- rectional i/o, depending on the value stored in (pxc2, pxc1 and pxc0). 7.5.2 pin declared as an alternate function input a single pin may be directly connected to several alternate function inputs. in this case, the user must select the required input mode (with the pxc2, pxc1, pxc0 bits) and enable the selected alternate function in the control register of the peripheral. no specific port configuration is re- quired to enable an alternate function input, since the input buffer is directly connected to each alter- nate function module on the shared pin. as more than one module can use the same input, it is up to the user software to enable the required module as necessary. parallel i/os remain operational even when using an alternate function input. the exception to this is when an i/o port bit is perma- nently assigned by hardware as an a/d bit. in this case , after software programming of the bit in af- od-ttl, the alternate function output is forced to logic level 1. the analog voltage level on the cor- responding pin is directly input to the a/d (see fig- ure 40 ). figure 40. a/d input configuration 7.5.3 pin declared as an alternate function output the user must select the af out configuration using the pxc2, pxc1, pxc0 bits. several alter- nate function outputs may drive a common pin. in such case, the alternate function output signals are logically anded before driving the common pin. the user must therefore enable the required alternate function output by software. warning : when a pin is connected both to an al- ternate function output and to an alternate function input, it should be noted that the output signal will always be present on the alternate function input. 7.6 i/o status after wfi, halt and reset the status of the i/o ports during the wait for in- terrupt, halt and reset operational modes is shown in the following table. the external memory interface ports are shown separately. if only the in- ternal memory is being used and the ports are act- ing as i/o, the status is the same as shown for the other i/o ports. input latch internal data bus i/o pin tristate input buffer output slave latch output master latch towards a/d converter gnd mode ext. mem - i/o ports i/o ports p0 p1, p2, p6, p9 wfi high imped- ance or next address (de- pending on the last memory op- eration per- formed on port) next address not affected (clock outputs running) halt high imped- ance next address not affected (clock outputs stopped) reset alternate function push- pull (romless device) bidirectional weak pull-up (high im- pedance when disa- bled in hardware).
76/268 - timer/watchdog (wdt) 8 on-chip peripherals 8.1 timer/watchdog (wdt) important note: this chapter is a generic descrip- tion of the wdt peripheral. however depending on the st9 device, some or all of wdt interface signals described may not be connected to exter- nal pins. for the list of wdt pins present on the st9 device, refer to the device pinout description in the first section of the data sheet. 8.1.1 introduction the timer/watchdog (wdt) peripheral consists of a programmable 16-bit timer and an 8-bit prescal- er. it can be used, for example, to: C generate periodic interrupts C measure input signal pulse widths C request an interrupt after a set number of events C generate an output signal waveform C act as a watchdog timer to monitor system in- tegrity the main wdt registers are: C control register for the input, output and interrupt logic blocks (wdtcr) C 16-bit counter register pair (wdthr, wdtlr) C prescaler register (wdtpr) the hardware interface consists of up to five sig- nals: C wdin external clock input C wdout square wave or pwm signal output C int0 external interrupt input C nmi non-maskable interrupt input C hw0sw1 hardware/software watchdog ena- ble. figure 41. timer/watchdog block diagram int0 1 input & clock control logic inen inmd1 inmd2 wdtpr 8-bit prescaler wdtrh, wdtrl 16-bit intclk/4 wdt outmd wrout output control logic interrupt control logic end of count reset top level interrupt request outen mux wdout 1 iaos tlis inta0 request nmi 1 wdgen hw0sw1 1 wdin 1 mux downcounter clock 1 pin not present on some st9 devices .
77/268 - timer/watchdog (wdt) timer/watchdog (contd) 8.1.2 functional description 8.1.2.1 external signals the hw0sw1 pin can be used to permanently en- able watchdog mode. refer to section 8.1.3.1 on page 78. the wdin input pin can be used in one of four modes: C event counter mode C gated external input mode C triggerable input mode C retriggerable input mode the wdout output pin can be used to generate a square wave or a pulse width modulated signal. an interrupt, generated when the wdt is running as the 16-bit timer/counter, can be used as a top level interrupt or as an interrupt source connected to channel a0 of the external interrupt structure (replacing the int0 interrupt input). the counter can be driven either by an external clock, or internally by intclk divided by 4. 8.1.2.2 initialisation the prescaler (wdtpr) and counter (wdtrl, wdtrh) registers must be loaded with initial val- ues before starting the timer/counter. if this is not done, counting will start with reset values. 8.1.2.3 start/stop the st_sp bit enables downcounting. when this bit is set, the timer will start at the beginning of the following instruction. resetting this bit stops the counter. if the counter is stopped and restarted, counting will resume from the last value unless a new con- stant has been entered in the timer registers (wdtrl, wdtrh). a new constant can be written in the wdtrh, wdtrl, wdtpr registers while the counter is running. the new value of the wdtrh, wdtrl registers will be loaded at the next end of count (eoc) condition while the new value of the wdtpr register will be effective immediately. end of count is when the counter is 0. when watchdog mode is enabled the state of the st_sp bit is irrelevant. 8.1.2.4 single/continuous mode the s_c bit allows selection of single or continu- ous mode.this mode bit can be written with the timer stopped or running. it is possible to toggle the s_c bit and start the counter with the same in- struction. single mode on reaching the end of count condition, the timer stops, reloads the constant, and resets the start/ stop bit. software can check the current status by reading this bit. to restart the timer, set the start/ stop bit. note: if the timer constant has been modified dur- ing the stop period, it is reloaded at start time. continuous mode on reaching the end of count condition, the coun- ter automatically reloads the constant and restarts. it is stopped only if the start/stop bit is reset. 8.1.2.5 input section if the timer/counter input is enabled (inen bit) it can count pulses input on the wdin pin. other- wise it counts the internal clock/4. for instance, when intclk = 24mhz, the end of count rate is: 2.79 seconds for maximum count (timer const. = ffffh, prescaler const. = ffh) 166 ns for minimum count (timer const. = 0000h, prescaler const. = 00h) the input pin can be used in one of four modes: C event counter mode C gated external input mode C triggerable input mode C retriggerable input mode the mode is configurable in the wdtcr. 8.1.2.6 event counter mode in this mode the timer is driven by the external clock applied to the input pin, thus operating as an event counter. the event is defined as a high to low transition of the input signal. spacing between trailing edges should be at least 8 intclk periods (or 333ns with intclk = 24mhz). counting starts at the next input event after the st_sp bit is set and stops when the st_sp bit is reset.
78/268 - timer/watchdog (wdt) timer/watchdog (contd) 8.1.2.7 gated input mode this mode can be used for pulse width measure- ment. the timer is clocked by intclk/4, and is started and stopped by means of the input pin and the st_sp bit. when the input pin is high, the tim- er counts. when it is low, counting stops. the maximum input pin frequency is equivalent to intclk/8. 8.1.2.8 triggerable input mode the timer (clocked internally by intclk/4) is started by the following sequence: C setting the start-stop bit, followed by C a high to low transition on the input pin. to stop the timer, reset the st_sp bit. 8.1.2.9 retriggerable input mode in this mode, the timer (clocked internally by intclk/4) is started by setting the st_sp bit. a high to low transition on the input pin causes counting to restart from the initial value. when the timer is stopped (st_sp bit reset), a high to low transition of the input pin has no effect. 8.1.2.10 timer/counter output modes output modes are selected by means of the out- en (output enable) and outmd (output mode) bits of the wdtcr register. no output mode (outen = 0) the output is disabled and the corresponding pin is set high, in order to allow other alternate func- tions to use the i/o pin. square wave output mode (outen = 1, outmd = 0) the timer outputs a signal with a frequency equal to half the end of count repetition rate on the wd- out pin. with an intclk frequency of 20mhz, this allows a square wave signal to be generated whose period can range from 400ns to 6.7 sec- onds. pulse width modulated output mode (outen = 1, outmd = 1) the state of the wrout bit is transferred to the output pin (wdout) at the end of count, and is held until the next end of count condition. the user can thus generate pwm signals by modifying the status of the wrout pin between end of count events, based on software counters decre- mented by the timer watchdog interrupt. 8.1.3 watchdog timer operation this mode is used to detect the occurrence of a software fault, usually generated by external inter- ference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence of operation. the watchdog, when enabled, resets the mcu, unless the pro- gram executes the correct write sequence before expiry of the programmed time period. the appli- cation program must be designed so as to correct- ly write to the wdtlr watchdog register at regu- lar intervals during all phases of normal operation. 8.1.3.1 hardware watchdog/software watchdog the hw0sw1 pin (when available) selects hard- ware watchdog or software watchdog. if hw0sw1 is held low: C the watchdog is enabled by hardware immedi- ately after an external reset. (note: software re- set or watchdog reset have no effect on the watchdog enable status). C the initial counter value (ffffh) cannot be mod- ified, however software can change the prescaler value on the fly. C the wdgen bit has no effect. (note: it is not forced low). if hw0sw1 is held high, or is not present: C the watchdog can be enabled by resetting the wdgen bit. 8.1.3.2 starting the watchdog in watchdog mode the timer is clocked by intclk/4. if the watchdog is software enabled, the time base must be written in the timer registers before enter- ing watchdog mode by resetting the wdgen bit. once reset, this bit cannot be changed by soft- ware. if the watchdog is hardware enabled, the time base is fixed by the reset value of the registers. resetting wdgen causes the counter to start, re- gardless of the value of the start-stop bit. in watchdog mode, only the prescaler constant may be modified. if the end of count condition is reached a system reset is generated.
79/268 - timer/watchdog (wdt) timer/watchdog (contd) 8.1.3.3 preventing watchdog system reset in order to prevent a system reset, the sequence aah, 55h must be written to wdtlr (watchdog timer low register). once 55h has been written, the timer reloads the constant and counting re- starts from the preset value. to reload the counter, the two writing operations must be performed sequentially without inserting other instructions that modify the value of the wdtlr register between the writing operations. the maximum allowed time between two reloads of the counter depends on the watchdog timeout period. 8.1.3.4 non-stop operation in watchdog mode, a halt instruction is regarded as illegal. execution of the halt instruction stops further execution by the cpu and interrupt ac- knowledgment, but does not stop intclk, cpu- clk or the watchdog timer, which will cause a system reset when the end of count condition is reached. furthermore, st_sp, s_c and the input mode selection bits are ignored. hence, regard- less of their status, the counter always runs in continuous mode, driven by the internal clock. the output mode should not be enabled, since in this context it is meaningless. figure 42. watchdog timer mode timer start counting wri te wdtrh,wdtrl wd en=0 write aah,55h into wdtrl reset software fail (e.g. infinite loop) or peripheral fail va00220 produce count reload value count g
80/268 - timer/watchdog (wdt) timer/watchdog (contd) 8.1.4 wdt interrupts the timer/watchdog issues an interrupt request at every end of count, when this feature is ena- bled. a pair of control bits, ia0s (eivr.1, interrupt a0 se- lection bit) and tlis (eivr.2, top level input se- lection bit) allow the selection of 2 interrupt sources (timer/watchdog end of count, or external pin) handled in two different ways, as a top level non maskable interrupt (software reset), or as a source for channel a0 of the external interrupt logic. a block diagram of the interrupt logic is given in figure 43 . note: software traps can be generated by setting the appropriate interrupt pending bit. table 17 below, shows all the possible configura- tions of interrupt/reset sources which relate to the timer/watchdog. a reset caused by the watchdog will set bit 6, wdgres of r242 - page 55 (clock flag regis- ter). see section clock control regis- ters . figure 43. interrupt sources table 17. interrupt configuration legend: wdg = watchdog function sw trap = software trap note: if ia0s and tlis = 0 (enabling the watchdog eoc as interrupt source for both top level and inta0 interrupts), only the inta0 interrupt is taken into account. timer watchdog reset wdgen (wcr.6) inta0 request ia0s (eivr.1) mux 0 1 int0 mux 0 1 top level interrupt request va00293 tlis (eivr.2) nmi control bits enabled sources operating mode wdgen ia0s tlis reset inta0 top level 0 0 0 0 0 0 1 1 0 1 0 1 wdg/ext reset wdg/ext reset wdg/ext reset wdg/ext reset sw trap sw trap ext pin ext pin sw trap ext pin sw trap ext pin watchdog watchdog watchdog watchdog 1 1 1 1 0 0 1 1 0 1 0 1 ext reset ext reset ext reset ext reset timer timer ext pin ext pin timer ext pin timer ext pin timer timer timer timer
81/268 - timer/watchdog (wdt) timer/watchdog (contd) 8.1.5 register description the timer/watchdog is associated with 4 registers mapped into group f, page 0 of the register file. wdthr : timer/watchdog high register wdtlr : timer/watchdog low register wdtpr : timer/watchdog prescaler register wdtcr : timer/watchdog control register three additional control bits are mapped in the fol- lowing registers on page 0: watchdog mode enable, (wcr.6) top level interrupt selection, (eivr.2) interrupt a0 channel selection, (eivr.1) note : the registers containing these bits also con- tain other functions. only the bits relevant to the operation of the timer/watchdog are shown here. counter register this 16-bit register (wdtlr, wdthr) is used to load the 16-bit counter value. the registers can be read or written on the fly. timer/watchdog high register (wdthr) r248 - read/write register page: 0 reset value: 1111 1111 (ffh) bits 7:0 = r[15:8] counter most significant bits . timer/watchdog low register (wdtlr) r249 - read/write register page: 0 reset value: 1111 1111b (ffh) bits 7:0 = r[7:0] counter least significant bits. timer/watchdog prescaler register (wdtpr) r250 - read/write register page: 0 reset value: 1111 1111 (ffh) bits 7:0 = pr[7:0] prescaler value. a programmable value from 1 (00h) to 256 (ffh). warning : in order to prevent incorrect operation of the timer/watchdog, the prescaler (wdtpr) and counter (wdtrl, wdtrh) registers must be ini- tialised before starting the timer/watchdog. if this is not done, counting will start with the reset (un-in- itialised) values. watchdog timer control register (wdtcr) r251- read/write register page: 0 reset value: 0001 0010 (12h) bit 7 = st_sp : start/stop bit . this bit is set and cleared by software. 0: stop counting 1: start counting (see warning above) bit 6 = s_c : single/continuous . this bit is set and cleared by software. 0: continuous mode 1: single mode bits 5:4 = inmd[1:2] : input mode selection bits . these bits select the input mode: 70 r15 r14 r13 r12 r11 r10 r9 r8 70 r7 r6 r5 r4 r3 r2 r1 r0 70 pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr0 70 st_sp s_c inmd1 inmd2 inen outmd wrout outen inmd1 inmd2 input mode 0 0 event counter 0 1 gated input (reset value) 1 0 triggerable input 1 1 retriggerable input
82/268 - timer/watchdog (wdt) timer/watchdog (contd) bit 3 = inen : input enable . this bit is set and cleared by software. 0: disable input section 1: enable input section bit 2 = outmd : output mode. this bit is set and cleared by software. 0: the output is toggled at every end of count 1: the value of the wrout bit is transferred to the output pin on every end of count if outen=1. bit 1 = wrout : write out . the status of this bit is transferred to the output pin when outmd is set; it is user definable to al- low pwm output (on reset wrout is set). bit 0 = outen : output enable bit . this bit is set and cleared by software. 0: disable output 1: enable output wait control register (wcr) r252 - read/write register page: 0 reset value: 0111 1111 (7fh) bit 6 = wdgen : watchdog enable (active low). resetting this bit via software enters the watch- dog mode. once reset, it cannot be set anymore by the user program. at system reset, the watch- dog mode is disabled. note: this bit is ignored if the hardware watchdog option is enabled by pin hw0sw1 (if available). external interrupt vector register (eivr) r246 - read/write register page: 0 reset value: xxxx 0110 (x6h) bit 2 = tlis : top level input selection . this bit is set and cleared by software. 0: watchdog end of count is tl interrupt source 1: nmi is tl interrupt source bit 1 = ia0s : interrupt channel a0 selection. this bit is set and cleared by software. 0: watchdog end of count is inta0 source 1: external interrupt pin is inta0 source warning : to avoid spurious interrupt requests, the ia0s bit should be accessed only when the in- terrupt logic is disabled (i.e. after the di instruc- tion). it is also necessary to clear any possible in- terrupt pending requests on channel a0 before en- abling this interrupt channel. a delay instruction (e.g. a nop instruction) must be inserted between the reset of the interrupt pending bit and the ia0s write instruction. other bits are described in the interrupt section. 70 xwdgenxxxxxx 70 x x x x x tlis ia0s x
83/268 - standard timer (stim) 8.2 standard timer (stim) important note: this chapter is a generic descrip- tion of the stim peripheral. depending on the st9 device, some or all of the interface signals de- scribed may not be connected to external pins. for the list of stim pins present on the particular st9 device, refer to the pinout description in the first section of the data sheet. 8.2.1 introduction the standard timer includes a programmable 16- bit down counter and an associated 8-bit prescaler with single and continuous counting modes capa- bility. the standard timer uses an input pin (stin) and an output (stout) pin. these pins, when available, may be independent pins or connected as alternate functions of an i/o port bit. stin can be used in one of four programmable in- put modes: C event counter, C gated external input mode, C triggerable input mode, C retriggerable input mode. stout can be used to generate a square wave or pulse width modulated signal. the standard timer is composed of a 16-bit down counter with an 8-bit prescaler. the input clock to the prescaler can be driven either by an internal clock equal to intclk divided by 4, or by clock2 derived directly from the external oscilla- tor, divided by device dependent prescaler value, thus providing a stable time reference independ- ent from the pll programming or by an external clock connected to the stin pin. the standard timer end of count condition is able to generate an interrupt which is connected to one of the external interrupt channels. the end of count condition is defined as the counter underflow, whenever 00h is reached. figure 44. standard timer block diagram n stout 1 external input & clock control logic inen inmd1 inmd2 stp 8-bit prescaler sth,stl 16-bit standard timer clock outmd1 outmd2 output control logic interrupt control logic end of count ints interrupt request clock2/x stin 1 interrupt 1 downcounter (see note 2) note 2: depending on device, the source of the input & clock control logic block may be permanently connected either to stin or the rccu signal clock2/x. in devices without stin and clock2, the intclk/4 mux note 1: pin not present on all st9 devices . inen bit must be held at 0.
84/268 - standard timer (stim) standard timer (contd) 8.2.2 functional description 8.2.2.1 timer/counter control start-stop count. the st-sp bit (stc.7) is used in order to start and stop counting. an instruction which sets this bit will cause the standard timer to start counting at the beginning of the next instruc- tion. resetting this bit will stop the counter. if the counter is stopped and restarted, counting will resume from the value held at the stop condi- tion, unless a new constant has been entered in the standard timer registers during the stop peri- od. in this case, the new constant will be loaded as soon as counting is restarted. a new constant can be written in sth, stl, stp registers while the counter is running. the new value of the sth and stl registers will be loaded at the next end of count condition, while the new value of the stp register will be loaded immedi- ately. warning: in order to prevent incorrect counting of the standard timer, the prescaler (stp) and counter (stl, sth) registers must be initialised before the starting of the timer. if this is not done, counting will start with the reset values (sth=ffh, stl=ffh, stp=ffh). single/continuous mode. the s-c bit (stc.6) selects between the single or continuous mode. single mode: at the end of count, the standard timer stops, reloads the constant and resets the start/stop bit (the user programmer can inspect the timer current status by reading this bit). setting the start/stop bit will restart the counter. continuous mode: at the end of the count, the counter automatically reloads the constant and re- starts. it is only stopped by resetting the start/stop bit. the s-c bit can be written either with the timer stopped or running. it is possible to toggle the s-c bit and start the standard timer with the same in- struction. 8.2.2.2 standard timer input modes (st9 devices with standard timer input stin) bits inmd2, inmd1 and inen are used to select the input modes. the input enable (inen) bit ena- bles the input mode selected by the inmd2 and inmd1 bits. if the input is disabled (inen="0"), the values of inmd2 and inmd1 are not taken into ac- count. in this case, this unit acts as a 16-bit timer (plus prescaler) directly driven by intclk/4 and transitions on the input pin have no effect. event counter mode (inmd1 = "0", inmd2 = "0") the standard timer is driven by the signal applied to the input pin (stin) which acts as an external clock. the unit works therefore as an event coun- ter. the event is a high to low transition on stin. spacing between trailing edges should be at least the period of intclk multiplied by 8 (i.e. the max- imum standard timer input frequency is 3 mhz with intclk = 24mhz). gated input mode (inmd1 = "0", inmd2 = 1) the timer uses the internal clock (intclk divided by 4) and starts and stops the timer according to the state of stin pin. when the status of the stin is high the standard timer count operation pro- ceeds, and when low, counting is stopped. triggerable input mode (inmd1 = 1, inmd2 = 0) the standard timer is started by: a) setting the start-stop bit, and b) a high to low (low trigger) transition on stin. in order to stop the standard timer in this mode, it is only necessary to reset the start-stop bit. retriggerable input mode (inmd1 = 1, inmd2 = 1) in this mode, when the standard timer is running (with internal clock), a high to low transition on stin causes the counting to start from the last constant loaded into the stl/sth and stp regis- ters. when the standard timer is stopped (st-sp bit equal to zero), a high to low transition on stin has no effect. 8.2.2.3 time base generator (st9 devices without standard timer input stin) for devices where stin is replaced by a connec- tion to clock2, the condition (inmd1 = 0, inmd2 = 0) will allow the standard timer to gen- erate a stable time base independent from the pll programming.
85/268 - standard timer (stim) standard timer (contd) 8.2.2.4 standard timer output modes output modes are selected using 2 bits of the stc register: outmd1 and outmd2. no output mode (outmd1 = 0, outmd2 = 0) the output is disabled and the corresponding pin is set high, in order to allow other alternate func- tions to use the i/o pin. square wave output mode (outmd1 = 0, outmd2 = 1) the standard timer toggles the state of the stout pin on every end of count condition. with intclk = 24mhz, this allows generation of a square wave with a period ranging from 333ns to 5.59 seconds. pwm output mode (outmd1 = 1) the value of the outmd2 bit is transferred to the stout output pin at the end of count. this al- lows the user to generate pwm signals, by modi- fying the status of outmd2 between end of count events, based on software counters decremented on the standard timer interrupt. 8.2.3 interrupt selection the standard timer may generate an interrupt re- quest at every end of count. bit 2 of the stc register (ints) selects the inter- rupt source between the standard timer interrupt and the external interrupt pin. thus the standard timer interrupt uses the interrupt channel and takes the priority and vector of the external inter- rupt channel. if ints is set to 1, the standard timer interrupt is disabled; otherwise, an interrupt request is gener- ated at every end of count. note: when enabling or disabling the standard timer interrupt (writing ints in the stc register) an edge may be generated on the interrupt chan- nel, causing an unwanted interrupt. to avoid this spurious interrupt request, the ints bit should be accessed only when the interrupt log- ic is disabled (i.e. after the di instruction). it is also necessary to clear any possible interrupt pending requests on the corresponding external interrupt channel before enabling it. a delay instruction (i.e. a nop instruction) must be inserted between the reset of the interrupt pending bit and the ints write instruction. 8.2.4 register mapping depending on the st9 device there may be up to 4 standard timers (refer to the block diagram in the first section of the data sheet). each standard timer has 4 registers mapped into page 11 in group f of the register file in the register description on the following page, register addresses refer to stim0 only. note: the four standard timers are not implement- ed on all st9 devices. refer to the block diagram of the device for the number of timers. std timer register register address stim0 sth0 r240 (f0h) stl0 r241 (f1h) stp0 r242 (f2h) stc0 r243 (f3h) stim1 sth1 r244 (f4h) stl1 r245 (f5h) stp1 r246 (f6h) stc1 r247 (f7h) stim2 sth2 r248 (f8h) stl2 r249 (f9h) stp2 r250 (fah) stc2 r251 (fbh) stim3 sth3 r252 (fch) stl3 r253 (fdh) stp3 r254 (feh) stc3 r255 (ffh)
86/268 - standard timer (stim) standard timer (contd) 8.2.5 register description counter high byte register (sth) r240 - read/write register page: 11 reset value: 1111 1111 (ffh) bits 7:0 = st.[15:8] : counter high-byte. counter low byte register (stl) r241 - read/write register page: 11 reset value: 1111 1111 (ffh) bits 7:0 = st.[7:0] : counter low byte. writing to the sth and stl registers allows the user to enter the standard timer constant, while reading it provides the counters current value. thus it is possible to read the counter on-the-fly. standard timer prescaler register (stp) r242 - read/write register page: 11 reset value: 1111 1111 (ffh) bits 7:0 = stp.[7:0] : prescaler. the prescaler value for the standard timer is pro- grammed into this register. when reading the stp register, the returned value corresponds to the programmed data instead of the current data. 00h: no prescaler 01h: divide by 2 ffh: divide by 256 standard timer control register (stc) r243 - read/write register page: 11 reset value: 0001 0100 (14h) bit 7 = st-sp : start-stop bit. this bit is set and cleared by software. 0: stop counting 1: start counting bit 6 = s-c : single-continuous mode select. this bit is set and cleared by software. 0: continuous mode 1: single mode bits 5:4 = inmd[1:2] : input mode selection. these bits select the input functions as shown in section 8.2.2.2 , when enabled by inen. bit 3 = inen : input enable. this bit is set and cleared by software. if neither the stin pin nor the clock2 line are present, inen must be 0. 0: input section disabled 1: input section enabled bit 2 = ints : interrupt selection. 0: standard timer interrupt enabled 1: standard timer interrupt is disabled and the ex- ternal interrupt pin is enabled. bits 1:0 = outmd[1:2] : output mode selection. these bits select the output functions as described in section 8.2.2.4 . 70 st.15 st.14 st.13 st.12 st.11 st.10 st.9 st.8 70 st.7 st.6 st.5 st.4 st.3 st.2 st.1 st.0 70 stp.7 stp.6 stp.5 stp.4 stp.3 stp.2 stp.1 stp.0 70 st-sp s-c inmd1 inmd2 inen ints outmd1 outmd2 inmd1 inmd2 mode 00 event counter mode 01 gated input mode 10 triggerable mode 11 retriggerable mode outmd1 outmd2 mode 00 no output mode 01 square wave output mode 1x pwm output mode
87/268 - multifunction timer (mft) 8.3 multifunction timer (mft) 8.3.1 introduction the multifunction timer (mft) peripheral offers powerful timing capabilities and features 12 oper- ating modes, including automatic pwm generation and frequency measurement. the mft comprises a 16-bit up/down counter driven by an 8-bit programmable prescaler. the in- put clock may be intclk/3 or an external source. the timer features two 16-bit comparison regis- ters, and two 16-bit capture/load/reload regis- ters. two input pins and two alternate function out- put pins are available. several functional configurations are possible, for instance: C 2 input captures on separate external lines, and 2 independent output compare functions with the counter in free-running mode, or 1 output com- pare at a fixed repetition rate. C 1 input capture, 1 counter reload and 2 inde- pendent output compares. C 2 alternate autoreloads and 2 independent out- put compares. C 2 alternate captures on the same external line and 2 independent output compares at a fixed repetition rate. when two mfts are present in an st9 device, a combined operating mode is available. an internal on-chip event signal can be used on some devices to control other on-chip peripherals. the two external inputs may be individually pro- grammed to detect any of the following: C rising edges C falling edges C both rising and falling edges figure 45. mft simplified block diagram
88/268 - multifunction timer (mft) multifunction timer (contd) the configuration of each input is programmed in the input control register. each of the two output pins can be driven from any of three possible sources: C compare register 0 logic C compare register 1 logic C overflow/underflow logic each of these three sources can cause one of the following four actions, independently, on each of the two outputs: C nop, set, reset, toggle in addition, an additional on-chip event signal can be generated by two of the three sources men- tioned above, i.e. over/underflow event and com- pare 0 event. this signal can be used internally to synchronise another on-chip peripheral. five maskable interrupt sources referring to an end of count condition, 2 input captures and 2 output compares, can generate 3 different interrupt re- quests (with hardware fixed priority), pointing to 3 interrupt routine vectors. two independent dma channels are available for rapid data transfer operations. each dma request (associated with a capture on the reg0r register, or with a compare on the cmp0r register) has pri- ority over an interrupt request generated by the same source. a swap mode is also available to allow high speed continuous transfers (see interrupt and dma chapter). figure 46. detailed block diagram
89/268 - multifunction timer (mft) multifunction timer (contd) 8.3.2 functional description the mft operating modes are selected by pro- gramming the timer control register (tcr) and the timer mode register (tmr). 8.3.2.1 trigger events a trigger event may be generated by software (by setting either the cp0 or the cp1 bits in the t_flagr register) or by an external source which may be programmed to respond to the rising edge, the falling edge or both by programming bits a0- a1 and b0-b1 in the t_icr register. this trigger event can be used to perform a capture or a load, depending on the timer mode (configured using the bits in table 21 ). an event on the txina input or setting the cp0 bit triggers a capture to, or a load from the reg0r register (except in bicapture mode, see section 8.3.2.11 ). an event on the txinb input or setting the cp1 bit triggers a capture to, or a load from the reg1r register. in addition, in the special case of "load from reg0r and monitor on reg1r", it is possible to use the txinb input as a trigger for reg0r." 8.3.2.2 one shot mode when the counter generates an overflow (in up- count mode), or an underflow (in down-count mode), that is to say when an end of count condi- tion is reached, the counter stops and no counter reload occurs. the counter may only be restarted by an external trigger on txina or b or a by soft- ware trigger on cp0 only. one shot mode is en- tered by setting the co bit in tmr. 8.3.2.3 continuous mode whenever the counter reaches an end of count condition, the counting sequence is automatically restarted and the counter is reloaded from reg0r (or from reg1r, when selected in biload mode). continuous mode is entered by resetting the c0 bit in tmr. 8.3.2.4 triggered and retriggered modes a triggered event may be generated by software (by setting either the cp0 or the cp1 bit in the t_flagr register), or by an external source which may be programmed to respond to the rising edge, the falling edge or both, by programming bits a0-a1 and b0-b1 in t_icr. in one shot and triggered mode, every trigger event arriving before an end of count, is masked. in one shot and retriggered mode, every trigger received while the counter is running, automatical- ly reloads the counter from reg0r. triggered/re- triggered mode is set by the ren bit in tmr. the txina input refers to reg0r and the txinb input refers to reg1r. warning . if the triggered mode is selected when the counter is in continuous mode, every trigger is disabled, it is not therefore possible to synchronise the counting cycle by hardware or software. 8.3.2.5 gated mode in this mode, counting takes place only when the external gate input is at a logic low level. the se- lection of txina or txinb as the gate input is made by programming the in0-in3 bits in t_icr. 8.3.2.6 capture mode the reg0r and reg1r registers may be inde- pendently set in capture mode by setting rm0 or rm1 in tmr, so that a capture of the current count value can be performed either on reg0r or on reg1r, initiated by software (by setting cp0 or cp1 in the t_flagr register) or by an event on the external input pins. warning . care should be taken when two soft- ware captures are to be performed on the same register. in this case, at least one instruction must be present between the first cp0/cp1 bit set and the subsequent cp0/cp1 bit reset instructions. 8.3.2.7 up/down mode the counter can count up or down depending on the state of the udc bit (up/down count) in tcr, or on the configuration of the external input pins, which have priority over udc (see input pin as- signment in t_icr). the udcs bit returns the counter up/down current status (see also the up/ down autodiscrimination mode in the input pin assignment section).
90/268 - multifunction timer (mft) multifunction timer (contd) 8.3.2.8 free running mode the timer counts continuously (in up or down mode) and the counter value simply overflows or underflows through ffffh or zero; there is no end of count condition as such, and no reloading takes place. this mode is automatically selected either in bi-capture mode or by setting register reg0r for a capture function (continuous mode must also be set). in autoclear mode, free running operation can be selected, with the possibility of choosing a maximum count value less than 2 16 before overflow or underflow (see autoclear mode). 8.3.2.9 monitor mode when the rm1 bit in tmr is reset, and the timer is not in bi-value mode, reg1r acts as a monitor, duplicating the current up or down counter con- tents, thus allowing the counter to be read on the fly. 8.3.2.10 autoclear mode a clear command forces the counter either to 0000h or to ffffh, depending on whether up- counting or downcounting is selected. the counter reset may be obtained either directly, through the ccl bit in tcr, or by entering the autoclear mode, through the ccp0 and ccmp0 bits in tcr. every capture performed on reg0r (if ccp0 is set), or every successful compare performed by cmp0r (if ccmp0 is set), clears the counter and reloads the prescaler. the clear on capture mode allows direct meas- urement of delta time between successive cap- tures on reg0r, while the clear on compare mode allows free running with the possibility of choosing a maximum count value before overflow or underflow which is less than 2 16 (see free run- ning mode). 8.3.2.11 bi-value mode depending on the value of the rm0 bit in tmr, the bi-load mode (rm0 reset) or the bi-capture mode (rm0 set) can be selected as illustrated in figure 18 below: table 18. bi-value modes a) biload mode the bi-load mode is entered by selecting the bi- value mode (bm set in tmr) and programming reg0r as a reload register (rm0 reset in tmr). at any end of count, counter reloading is per- formed alternately from reg0r and reg1r, (a low level for bm bit always sets reg0r as the cur- rent register, so that, after a low to high transition of bm bit, the first reload is always from reg0r). tmr bits timer operating modes rm0 rm1 bm 0 1 x x 1 1 bi-load mode bi-capture mode
91/268 - multifunction timer (mft) multifunction timer (contd) every software or external trigger event on reg0r performs a reload from reg0r resetting the biload cycle. in one shot mode (reload initiat- ed by software or by an external trigger), reloading is always from reg0r. b) bicapture mode the bicapture mode is entered by selecting the bi- value mode (the bm bit in tmr is set) and by pro- gramming reg0r as a capture register (the rm0 bit in tmr is set). interrupt generation can be configured as an and or or function of the two capture events. this is configured by the a0 bit in the t_flagr register. every capture event, software simulated (by set- ting the cp0 flag) or coming directly from the txi- na input line, captures the current counter value alternately into reg0r and reg1r. when the bm bit is reset, reg0r is the current register, so that the first capture, after resetting the bm bit, is always into reg0r. 8.3.2.12 parallel mode when two mfts are present on an st9 device, the parallel mode is entered when the eck bit in the tmr register of timer 1 is set. the timer 1 prescaler input is internally connected to the timer 0 prescaler output. timer 0 prescaler input is con- nected to the system clock line. by loading the prescaler register of timer 1 with the value 00h the two timers (timer 0 and timer 1) are driven by the same frequency in parallel mode. in this mode the clock frequency may be divided by a factor in the range from 1 to 2 16 . 8.3.2.13 autodiscriminator mode the phase difference sign of two overlapping puls- es (respectively on txinb and txina) generates a one step up/down count, so that the up/down con- trol and the counter clock are both external. the setting of the udc bit in the tcr register has no effect in this configuration. figure 47. parallel mode description prescaler 0 prescaler 1 mft1 intclk/3 note: mft 1 is not available on all devices. refer to counter block diagram and register map. the device mft0 counter
92/268 - multifunction timer (mft) multifunction timer (contd) 8.3.3 input pin assignment the two external inputs (txina and txinb) of the timer can be individually configured to catch a par- ticular external event (i.e. rising edge, falling edge, or both rising and falling edges) by programming the two relevant bits (a0, a1 and b0, b1) for each input in the external input control register (t_icr). the 16 different functional modes of the two exter- nal inputs can be selected by programming bits in0 - in3 of the t_icr, as illustrated in figure 19 table 19. input pin function some choices relating to the external input pin as- signment are defined in conjunction with the rm0 and rm1 bits in tmr. for input pin assignment codes which use the in- put pins as trigger inputs (except for code 1010, trigger up:trigger down), the following conditions apply: C a trigger signal on the txina input pin performs an u/d counter load if rm0 is reset, or an exter- nal capture if rm0 is set. C a trigger signal on the txinb input pin always performs an external capture on reg1r. the txinb input pin is disabled when the bivalue mode is set. note : for proper operation of the external input pins, the following must be observed: C the minimum external clock/trigger pulse width must not be less than the system clock (intclk) period if the input pin is programmed as rising or falling edge sensitive. C the minimum external clock/trigger pulse width must not be less than the prescaler clock period (intclk/3) if the input pin is programmed as ris- ing and falling edge sensitive (valid also in auto discrimination mode). C the minimum delay between two clock/trigger pulse active edges must be greater than the prescaler clock period (intclk/3), while the minimum delay between two consecutive clock/ trigger pulses must be greater than the system clock (intclk) period. C the minimum gate pulse width must be at least twice the prescaler clock period (intclk/3). C in autodiscrimination mode, the minimum delay between the input pin a pulse edge and the edge of the input pin b pulse, must be at least equal to the system clock (intclk) period. C if a number, n, of external pulses must be count- ed using a compare register in external clock mode, then the compare register must be load- ed with the value [x +/- (n-1)], where x is the starting counter value and the sign is chosen de- pending on whether up or down count mode is selected. i c reg. in3-in0 bits txina input function txinb input function 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 not used not used gate gate not used trigger gate trigger clock up up/down trigger up up/down autodiscr. trigger ext. clock trigger not used trigger not used trigger ext. clock not used ext. clock trigger clock down ext. clock trigger down not used autodiscr. ext. clock trigger gate
93/268 - multifunction timer (mft) multifunction timer (contd) 8.3.3.1 txina = i/o - txinb = i/o input pins a and b are not used by the timer. the counter clock is internally generated and the up/ down selection may be made only by software via the udc (software up/down) bit in the tcr regis- ter. 8.3.3.2 txina = i/o - txinb = trigger the signal applied to input pin b acts as a trigger signal on reg1r register. the prescaler clock is internally generated and the up/down selection may be made only by software via the udc (soft- ware up/down) bit in the tcr register. 8.3.3.3 txina = gate - txinb = i/o the signal applied to input pin a acts as a gate sig- nal for the internal clock (i.e. the counter runs only when the gate signal is at a low level). the counter clock is internally generated and the up/down con- trol may be made only by software via the udc (software up/down) bit in the tcr register. 8.3.3.4 txina = gate - txinb = trigger both input pins a and b are connected to the timer, with the resulting effect of combining the actions relating to the previously described configurations. 8.3.3.5 txina = i/o - txinb = ext. clock the signal applied to input pin b is used as the ex- ternal clock for the prescaler. the up/down selec- tion may be made only by software via the udc (software up/down) bit in the tcr register. 8.3.3.6 txina = trigger - txinb = i/o the signal applied to input pin a acts as a trigger for reg0r, initiating the action for which the reg- ister was programmed (i.e. a reload or capture). the prescaler clock is internally generated and the up/down selection may be made only by software via the udc (software up/down) bit in the tcr register. (*) the timer is in one shot mode and regor in reload mode 8.3.3.7 txina = gate - txinb = ext. clock the signal applied to input pin b, gated by the sig- nal applied to input pin a, acts as external clock for the prescaler. the up/down control may be made only by software action through the udc bit in the tcr register. 8.3.3.8 txina = trigger - txinb = trigger the signal applied to input pin a (or b) acts as trig- ger signal for reg0r (or reg1r), initiating the action for which the register has been pro- grammed. the counter clock is internally generat- ed and the up/down selection may be made only by software via the udc (software up/down) bit in the tcr register.
94/268 - multifunction timer (mft) multifunction timer (contd) 8.3.3.9 txina = clock up - txinb = clock down the edge received on input pin a (or b) performs a one step up (or down) count, so that the counter clock and the up/down control are external. setting the udc bit in the tcr register has no effect in this configuration, and input pin b has priority on input pin a. 8.3.3.10 txina = up/down - txinb = ext clock an high (or low) level applied to input pin a sets the counter in the up (or down) count mode, while the signal applied to input pin b is used as clock for the prescaler. setting the udc bit in the tcr reg- ister has no effect in this configuration. 8.3.3.11 txina = trigger up - txinb = trigger down up/down control is performed through both input pins a and b. a edge on input pin a sets the up count mode, while a edge on input pin b (which has priority on input pin a) sets the down count mode. the counter clock is internally generated, and setting the udc bit in the tcr register has no effect in this configuration. 8.3.3.12 txina = up/down - txinb = i/o an high (or low) level of the signal applied on in- put pin a sets the counter in the up (or down) count mode. the counter clock is internally generated. setting the udc bit in the tcr register has no ef- fect in this configuration.
95/268 - multifunction timer (mft) multifunction timer (contd) 8.3.3.13 autodiscrimination mode the phase between two pulses (respectively on in- put pin b and input pin a) generates a one step up (or down) count, so that the up/down control and the counter clock are both external. thus, if the ris- ing edge of txinb arrives when txina is at a low level, the timer is incremented (no action if the ris- ing edge of txinb arrives when txina is at a high level). if the falling edge of txinb arrives when txina is at a low level, the timer is decremented (no action if the falling edge of txinb arrives when txina is at a high level). setting the udc bit in the tcr register has no ef- fect in this configuration. 8.3.3.14 txina = trigger - txinb = ext. clock the signal applied to input pin a acts as a trigger signal on reg0r, initiating the action for which the register was programmed (i.e. a reload or cap- ture), while the signal applied to input pin b is used as the clock for the prescaler. (*) the timer is in one shot mode and reg0r in reload mode 8.3.3.15 txina = ext. clock - txinb = trigger the signal applied to input pin b acts as a trigger, performing a capture on reg1r, while the signal applied to input pin a is used as the clock for the prescaler. 8.3.3.16 txina = trigger - txinb = gate the signal applied to input pin a acts as a trigger signal on reg0r, initiating the action for which the register was programmed (i.e. a reload or cap- ture), while the signal applied to input pin b acts as a gate signal for the internal clock (i.e. the counter runs only when the gate signal is at a low level).
96/268 - multifunction timer (mft) multifunction timer (contd) 8.3.4 output pin assignment two external outputs are available when pro- grammed as alternate function outputs of the i/o pins. two registers output a control register (oacr) and output b control register (obcr) define the driver for the outputs and the actions to be per- formed. each of the two output pins can be driven from any of the three possible sources: C compare register 0 event logic C compare register 1 event logic C overflow/underflow event logic. each of these three sources can cause one of the following four actions on any of the two outputs: C nop C set C reset C toggle furthermore an on chip event signal can be driv- en by two of the three sources: the over/under- flow event and compare 0 event by programming the cev bit of the oacr register and the oev bit of obcr register respectively. this signal can be used internally to synchronise another on-chip pe- ripheral. output waveforms depending on the programming of oacr and ob- cr, the following example waveforms can be gen- erated on txouta and txoutb pins. for a configuration where txouta is driven by the over/underflow (ouf) and the compare 0 event (cm0), and txoutb is driven by the over/under- flow and compare 1 event (cm1): oacr is programmed with txouta preset to 0, ouf sets txouta, cm0 resets txouta and cm1 does not affect the output. obcr is programmed with txoutb preset to 0, ouf sets txoutb, cm1 resets txoutb while cm0 does not affect the output. for a configuration where txouta is driven by the over/underflow, by compare 0 and by compare 1; txoutb is driven by both compare 0 and com- pare 1. oacr is programmed with txouta pre- set to 0. ouf toggles output 0, as do cm0 and cm1. obcr is programmed with txoutb preset to 1. ouf does not affect the output; cm0 resets txoutb and cm1 sets it. oacr = [101100x0] obcr = [111000x0] t0outa t0outb ouf comp1 ouf comp1 ouf comp0 ouf comp0 oacr = [010101x0] obcr = [100011x1] t0outa t0outb comp1 comp1 ouf ouf comp0 comp0 comp0 comp0 comp1 comp1
97/268 - multifunction timer (mft) multifunction timer (contd) for a configuration where txouta is driven by the over/underflow and by compare 0, and txoutb is driven by the over/underflow and by compare 1. oacr is programmed with txouta preset to 0. ouf sets txouta while cm0 resets it, and cm1 has no effect. obcr is programmed with tx- outb preset to 1. ouf toggles txoutb, cm1 sets it and cm0 has no effect. for a configuration where txouta is driven by the over/underflow and by compare 0, and txoutb is driven by compare 0 and 1. oacr is pro- grammed with txouta preset to 0. ouf sets txouta, cm0 resets it and cm1 has no effect. obcr is programmed with txoutb preset to 0. ouf has no effect, cm0 sets txoutb and cm1 toggles it. output waveform samples in biload mode txouta is programmed to monitor the two time intervals, t1 and t2, of the biload mode, while tx- outb is independent of the over/underflow and is driven by the different values of compare 0 and compare 1. oacr is programmed with txouta preset to 0. ouf toggles the output and cm0 and cm1 do not affect txouta. obcr is programmed with txoutb preset to 0. ouf has no effect, while cm1 resets txoutb and cm0 sets it. depending on the cm1/cm0 values, three differ- ent sample waveforms have been drawn based on the above mentioned configuration of obcr. in the last case, with a different programmed value of obcr, only compare 0 drives txoutb, toggling the output. note (*) depending on the cmp1r/cmp0r values oacr = [101100x0] obcr = [000111x0] t0outa t0outb ouf ouf comp0 comp0 comp0 comp0 comp1 comp1
98/268 - multifunction timer (mft) multifunction timer (contd) 8.3.5 interrupt and dma 8.3.5.1 timer interrupt the timer has 5 different interrupt sources, be- longing to 3 independent groups, which are as- signed to the following interrupt vectors: table 20. timer interrupt structure the three least significant bits of the vector pointer address represent the relative priority assigned to each group, where 000 represents the highest pri- ority level. these relative priorities are fixed by hardware, according to the source which gener- ates the interrupt request. the 5 most significant bits represent the general priority and are pro- grammed by the user in the interrupt vector reg- ister (t_ivr). each source can be masked by a dedicated bit in the interrupt/dma mask register (idmr) of each timer, as well as by a global mask enable bit (id- mr.7) which masks all interrupts. if an interrupt request (cm0 or cp0) is present be- fore the corresponding pending bit is reset, an overrun condition occurs. this condition is flagged in two dedicated overrun bits, relating to the comp0 and capt0 sources, in the timer flag reg- ister (t_flagr). 8.3.5.2 timer dma two independent dma channels, associated with comp0 and capt0 respectively, allow dma trans- fers from register file or memory to the comp0 register, and from the capt0 register to register file or memory). if dma is enabled, the capt0 and comp0 interrupts are generated by the corre- sponding dma end of block event. their priority is set by hardware as follows: C compare 0 destination lower priority C capture 0 source higher priority the two dma request sources are independently maskable by the cp0d and cm0d dma mask bits in the idmr register. the two dma end of block interrupts are inde- pendently enabled by the cp0i and cm0i interrupt mask bits in the idmr register. 8.3.5.3 dma pointers the 6 programmable most significant bits of the dma counter pointer register (dcpr) and of the dma address pointer register (dapr) are com- mon to both channels (comp0 and capt0). the comp0 and capt0 address pointers are mapped as a pair in the register file, as are the comp0 and capt0 dma counter pair. in order to specify either the capt0 or the comp0 pointers, according to the channel being serviced, the timer resets address bit 1 for capt0 and sets it for comp0, when the d0 bit in the dcpr regis- ter is equal to zero (word address in register file). in this case (transfers between peripheral registers and memory), the pointers are split into two groups of adjacent address and counter pairs respectively. for peripheral register to register transfers (select- ed by programming 1 into bit 0 of the dcpr reg- ister), only one pair of pointers is required, and the pointers are mapped into one group of adjacent positions. the dma address pointer register (dapr) is not used in this case, but must be considered re- served. figure 48. pointer mapping for transfers between registers and memory interrupt source vector address comp 0 comp 1 xxxx x110 capt 0 capt 1 xxxx x100 overflow/underflow xxxx x000 register file address pointers comp0 16 bit addr pointer yyyyyy11(l) yyyyyy10(h) capt0 16 bit addr pointer yyyyyy01(l) yyyyyy00(h) dma counters comp0 dma 16 bit counter xxxxxx11(l) xxxxxx10(h) capt0 dma 16 bit counter xxxxxx01(l) xxxxxx00(h)
99/268 - multifunction timer (mft) multifunction timer (contd) figure 49. pointer mapping for register to register transfers 8.3.5.4 dma transaction priorities each timer dma transaction is a 16-bit operation, therefore two bytes must be transferred sequen- tially, by means of two dma transfers. in order to speed up each word transfer, the second byte transfer is executed by automatically forcing the peripheral priority to the highest level (000), re- gardless of the previously set level. it is then re- stored to its original value after executing the transfer. thus, once a request is being serviced, its hardware priority is kept at the highest level re- gardless of the other timer internal sources, i.e. once a comp0 request is being serviced, it main- tains a higher priority, even if a capt0 request oc- curs between the two byte transfers. 8.3.5.5 dma swap mode after a complete data table transfer, the transac- tion counter is reset and an end of block (eob) condition occurs, the block transfer is completed. the end of block interrupt routine must at this point reload both address and counter pointers of the channel referred to by the end of block inter- rupt source, if the application requires a continu- ous high speed data flow. this procedure causes speed limitations because of the time required for the reload routine. the swap feature overcomes this drawback, al- lowing high speed continuous transfers. bit 2 of the dma counter pointer register (dcpr) and of the dma address pointer register (dapr), tog- gles after every end of block condition, alternately providing odd and even address (d2-d7) for the pair of pointers, thus pointing to an updated pair, after a block has been completely transferred. this allows the user to update or read the first block and to update the pointer values while the second is being transferred. these two toggle bits are soft- ware writable and readable, mapped in dcpr bit 2 for the cm0 channel, and in dapr bit 2 for the cp0 channel (though a dma event on a channel, in swap mode, modifies a field in dapr and dcpr common to both channels, the dapr/ dcpr content used in the transfer is always the bit related to the correct channel). swap mode can be enabled by the swen bit in the idcr register. warning : enabling swap mode affects both channels (cm0 and cp0). register file 8 bit counter xxxxxx11 compare 0 8 bit addr pointer xxxxxx10 8 bit counter xxxxxx01 capture 0 8 bit addr pointer xxxxxx00
100/268 - multifunction timer (mft) multifunction timer (contd) 8.3.5.6 dma end of block interrupt routine an interrupt request is generated after each block transfer (eob) and its priority is the same as that assigned in the usual interrupt request, for the two channels. as a consequence, they will be serviced only when no dma request occurs, and will be subject to a possible ouf interrupt request, which has higher priority. the following is a typical eob procedure (with swap mode enabled): C test toggle bit and jump. C reload pointers (odd or even depending on tog- gle bit status). C reset eob bit: this bit must be reset only after the old pair of pointers has been restored, so that, if a new eob condition occurs, the next pair of pointers is ready for swapping. C verify the software protection condition (see section 8.3.5.7 ). C read the corresponding overrun bit: this con- firms that no dma request has been lost in the meantime. C reset the corresponding pending bit. C reenable dma with the corresponding dma mask bit (must always be done after resetting the pending bit) C return. warning : the eob bits are read/write only for test purposes. writing a logical 1 by software (when the swen bit is set) will cause a spurious interrupt request. these bits are normally only re- set by software. 8.3.5.7 dma software protection a second eob condition may occur before the first eob routine is completed, this would cause a not yet updated pointer pair to be addressed, with con- sequent overwriting of memory. to prevent these errors, a protection mechanism is provided, such that the attempted setting of the eob bit before it has been reset by software will cause the dma mask on that channel to be reset (dma disabled), thus blocking any further dma operation. as shown above, this mask bit should always be checked in each eob routine, to ensure that all dma transfers are properly served. 8.3.6 register description note: in the register description on the following pages, register and page numbers are given using the example of timer 0. on devices with more than one timer, refer to the device register map for the adresses and page numbers.
101/268 - multifunction timer (mft) multifunction timer (contd) capture load 0 high register (reg0hr) r240 - read/write register page: 10 reset value: undefined this register is used to capture values from the up/down counter or load preset values (msb). capture load 0 low register (reg0lr) r241 - read/write register page: 10 reset value: undefined this register is used to capture values from the up/down counter or load preset values (lsb). capture load 1 high register (reg1hr) r242 - read/write register page: 10 reset value: undefined this register is used to capture values from the up/down counter or load preset values (msb). capture load 1 low register (reg1lr) r243 - read/write register page: 10 reset value: undefined this register is used to capture values from the up/down counter or load preset values (lsb). compare 0 high register (cmp0hr) r244 - read/write register page: 10 reset value: 0000 0000 (00h) this register is used to store the msb of the 16-bit value to be compared to the up/down counter content. compare 0 low register (cmp0lr) r245 - read/write register page: 10 reset value: 0000 0000 (00h) this register is used to store the lsb of the 16-bit value to be compared to the up/down counter content. compare 1 high register (cmp1hr) r246 - read/write register page: 10 reset value: 0000 0000 (00h) this register is used to store the msb of the 16-bit value to be compared to the up/down counter content. compare 1 low register (cmp1lr) r247 - read/write register page: 10 reset value: 0000 0000 (00h) this register is used to store the lsb of the 16-bit value to be compared to the up/down counter content. 70 r15 r14 r13 r12 r11 r10 r9 r8 70 r7 r6 r5 r4 r3 r2 r1 r0 70 r15 r14 r13 r12 r11 r10 r9 r8 70 r7 r6 r5 r4 r3 r2 r1 r0 70 r15 r14 r13 r12 r11 r10 r9 r8 70 r7 r6 r5 r4 r3 r2 r1 r0 70 r15 r14 r13 r12 r11 r10 r9 r8 70 r7 r6 r5 r4 r3 r2 r1 r0
102/268 - multifunction timer (mft) multifunction timer (contd) timer control register (tcr) r248 - read/write register page: 10 reset value: 0000 0000 (00h) bit 7 = cen : counter enable . this bit is anded with the global counter enable bit (gcen) in the cicr register (r230). the gcen bit is set after the reset cycle. 0: stop the counter and prescaler 1: start the counter and prescaler (without reload). note: even if cen=0, capture and loading will take place on a trigger event. bit 6 = ccp0 : clear on capture . 0: no effect 1: clear the counter and reload the prescaler on a reg0r or reg1r capture event bit 5 = ccmp0 : clear on compare . 0: no effect 1: clear the counter and reload the prescaler on a cmp0r compare event bit 4 = ccl : counter clear . this bit is reset by hardware after being set by software (this bit always returns 0 when read). 0: no effect 1: clear the counter without generating an inter- rupt request bit 3 = udc : up/down software selection . if the direction of the counter is not fixed by hard- ware (txina and/or txinb pins, see par. 10.3) it can be controlled by software using the udc bit. 0: down counting 1: up counting bit 2 = udcs : up/down count status . this bit is read only and indicates the direction of the counter. 0: down counting 1: up counting bit 1 = of0 : ovf/unf state . this bit is read only. 0: no overflow or underflow occurred 1: overflow or underflow occurred during a cap- ture on register 0 bit 0 = cs counter status . this bit is read only and indicates the status of the counter. 0: counter halted 1: counter running 70 cen ccp 0 ccmp 0 ccl udc udc s of0 cs
103/268 - multifunction timer (mft) multifunction timer (contd) timer mode register (tmr) r249 - read/write register page: 10 reset value: 0000 0000 (00h) bit 7 = oe1 : output 1 enable. 0: disable the output 1 (txoutb pin) and force it high. 1: enable the output 1 (txoutb pin) the relevant i/o bit must also be set to alternate function bit 6 = oe0 : output 0 enable. 0: disable the output 0 (txouta pin) and force it high 1: enable the output 0 (txouta pin). the relevant i/o bit must also be set to alternate function bit 5 = bm : bivalu e mode . this bit works together with the rm1 and rm0 bits to select the timer operating mode (see table 21 ). 0: disable bivalue mode 1: enable bivalue mode bit 4 = rm1 : reg1r mode . this bit works together with the bm and rm0 bits to select the timer operating mode. refer to table 21 . note: this bit has no effect when the bivalue mode is enabled (bm=1). bit 3 = rm0 : reg0r mode . this bit works together with the bm and rm1 bits to select the timer operating mode. refer to table 21 . table 21. timer operating modes bit 2 = eck timer clock control . 0: the prescaler clock source is selected depend- ing on the in0 - in3 bits in the t_icr register 1: enter parallel mode (for timer 1 and timer 3 only, no effect for timer 0 and 2). see section 8.3.2.12 . bit 1 = ren : retrigger mode . 0: enable retriggerable mode 1: disable retriggerable mode bit 0 = co : continous/one shot mode . 0: continuous mode (with autoreload on end of count condition) 1: one shot mode 70 oe1 oe0 bm rm1 rm0 eck ren c0 tmr bits timer operating modes bm rm1 rm0 1 x 0 biload mode 1 x 1 bicapture mode 00 0 load from reg0r and monitor on reg1r 01 0 load from reg0r and capture on reg1r 00 1 capture on reg0r and monitor on reg1r 0 1 1 capture on reg0r and reg1r
104/268 - multifunction timer (mft) multifunction timer (contd) external input control register (t_icr) r250 - read/write register page: 10 reset value: 0000 0000 (00h) bits 7:4 = in[3:0] : input pin function. these bits are set and cleared by software. bits 3:2 = a[0:1] : txina pin event . these bits are set and cleared by software. bits 1:0 = b[0:1]: txinb pin event . these bits are set and cleared by software. prescaler register (prsr) r251 - read/write register page: 10 reset value: 0000 0000 (00h) this register holds the preset value for the 8-bit prescaler. the prsr content may be modified at any time, but it will be loaded into the prescaler at the following prescaler underflow, or as a conse- quence of a counter reload (either by software or upon external request). following a reset condition, the prescaler is au- tomatically loaded with 00h, so that the prescaler divides by 1 and the maximum counter clock is generated (crystal oscillator clock frequency divid- ed by 6 when moder.5 = div2 bit is set). the binary value programmed in the prsr regis- ter is equal to the divider value minus one. for ex- ample, loading prsr with 24 causes the prescal- er to divide by 25. 70 in3 in2 in1 in0 a0 a1 b0 b1 in[3:0] bits txina pin function txinb input pin function 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 not used not used gate gate not used trigger gate trigger clock up up/down trigger up up/down autodiscr. trigger ext. clock trigger not used trigger not used trigger ext. clock not used ext. clock trigger clock down ext. clock trigger down not used autodiscr. ext. clock trigger gate a0 a1 txina pin event 0 0 1 1 0 1 0 1 no operation falling edge sensitive rising edge sensitive rising and falling edges b0 b1 txinb pin event 0 0 1 1 0 1 0 1 no operation falling edge sensitive rising edge sensitive rising and falling edges 70 p7 p6 p5 p4 p3 p2 p1 p0
105/268 - multifunction timer (mft) multifunction timer (contd) output a control register (oacr) r252 - read/write register page: 10 reset value: 0000 0000 bits 7:6 = c0e[0:1] : comp0 action bits . these bits are set and cleared by software. they configure the action to be performed on the tx- outa pin when a successful compare of the cmp0r register occurs. refer to table 22 for the list of actions that can be configured. bits 5:4 = c1e[0:1]: comp1 action bits . these bits are set and cleared by software. they configure the action to be performed on the tx- outa pin when a successful compare of the cmp1r register occurs. refer to table 22 for the list of actions that can be configured. bits 3:2 = oue[0:1] : ovf/unf action bits . these bits are set and cleared by software. they configure the action to be performed on the tx- outa pin when an overflow or underflow of the u/d counter occurs. refer to table 22 for the list of actions that can be configured. table 22. output a action bits notes: C xx stands for c0, c1 or ou. C whenever more than one event occurs simulta- neously, action bit 0 will be the result of anding action bit 0 of all simultaneous events and action bit 1 will be the result of anding action bit 1 of all simultaneous events. bit 1 = cev : on-chip event on cmp0r . this bit is set and cleared by software. 0: no action 1: a successful compare on cmp0r activates the on-chip event signal (a single pulse is generat- ed) bit 0 = op : txouta preset value . this bit is set and cleared by software and by hard- ware. the value of this bit is the preset value of the txouta pin. reading this bit returns the current state of the txouta pin (useful when it is selected in toggle mode). 70 c0e0 c0e1 c1e0 c1e1 oue0 oue1 cev 0p xxe0 xxe1 action on txouta pin when an xx event occurs 0 0 set 0 1 toggle 1 0 reset 1 1 nop
106/268 - multifunction timer (mft) multifunction timer (contd) output b control register (obcr) r253 - read/write register page: 10 reset value: 0000 0000 (00h) bits 7:6 = c0e[0:1] : comp0 action bits . these bits are set and cleared by software. they configure the type of action to be performed on the txoutb output pin when successful compare of the cmp0r register occurs. refer to table 23 for the list of actions that can be configured. bits 5:4 = c0e[0:1]: comp1 action bits . these bits are set and cleared by software. they configure the type of action to be performed on the txoutb output pin when a successful compare of the cmp1r register occurs. refer to table 23 for the list of actions that can be configured. bits 3:2 = oue[0:1] : ovf/unf action bits . these bits are set and cleared by software.they configure the type of action to be performed on the txoutb output pin when an overflow or under- flow on the u/d counter occurs. refer to table 23 for the list of actions that can be configured. table 23. output b action bits notes: C xx stands for c0, c1 or ou. C whenever more than one event occurs simulta- neously, action bit 0 will be the result of anding action bit 0 of all simultaneous events and action bit 1 will be the result of anding action bit 1 of all simultaneous events. bit 1 = oev : on-chip event on ovf/unf . this bit is set and cleared by software. 0: no action 1: an underflow/overflow activates the on-chip event signal (a single pulse is generated) bit 0 = op : txoutb preset value . this bit is set and cleared by software and by hard- ware. the value of this bit is the preset value of the txoutb pin. reading this bit returns the current state of the txoutb pin (useful when it is selected in toggle mode). 70 c0e0 c0e1 c1e0 c1e1 oue0 oue1 oev 0p xxe0 xxe1 action on the txoutb pin when an xx event occurs 0 0 set 0 1 toggle 1 0 reset 1 1 nop
107/268 - multifunction timer (mft) multifunction timer (contd) flag register (t_flagr) r254 - read/write register page: 10 reset value: 0000 0000 (00h) bit 7 = cp0 : capture 0 flag. this bit is set by hardware after a capture on reg0r register. an interrupt is generated de- pending on the value of the gtien, cp0i bits in the idmr register and the a0 bit in the t_flagr register. the cp0 bit must be cleared by software. setting by software acts as a software load/cap- ture to/from the reg0r register. 0: no capture 0 event 1: capture 0 event occurred bit 6 = cp1 : capture 1 flag . this bit is set by hardware after a capture on reg1r register. an interrupt is generated de- pending on the value of the gtien, cp0i bits in the idmr register and the a0 bit in the t_flagr register. the cp1 bit must be cleared by software. setting by software acts as a capture event on the reg1r register, except when in bicapture mode. 0: no capture 1 event 1: capture 1 event occurred bit 5 = cm0 : compare 0 flag . this bit is set by hardware after a successful com- pare on the cmp0r register. an interrupt is gener- ated if the gtien and cm0i bits in the idmr reg- ister are set. the cm0 bit is cleared by software. 0: no compare 0 event 1: compare 0 event occurred bit 4 = cm1 : compare 1 flag. this bit is set after a successful compare on cmp1r register. an interrupt is generated if the gtien and cm1i bits in the idmr register are set. the cm1 bit is cleared by software. 0: no compare 1 event 1: compare 1 event occurred bit 3 = ouf : overflow/underflow . this bit is set by hardware after a counter over/ underflow condition. an interrupt is generated if gtien and oui=1 in the idmr register. the ouf bit is cleared by software. 0: no counter overflow/underflow 1: counter overflow/underflow bit 2 = ocp0 : overrun on capture 0. this bit is set by hardware when more than one int/dma requests occur before the cp0 flag is cleared by software or whenever a capture is sim- ulated by setting the cp0 flag by software. the ocp0 flag is cleared by software. 0: no capture 0 overrun 1: capture 0 overrun bit 1 = ocm0 : overrun on compare 0. this bit is set by hardware when more than one int/dma requests occur before the cm0 flag is cleared by software.the ocm0 flag is cleared by software. 0: no compare 0 overrun 1: compare 0 overrun bit 0 = a0 : capture interrupt function . this bit is set and cleared by software. 0: configure the capture interrupt as an or func- tion of reg0r/reg1r captures 1: configure the capture interrupt as an and func- tion of reg0r/reg1r captures note: when a0 is set, both cp0i and cp1i in the idmr register must be set to enable both capture interrupts. 70 cp0 cp1 cm0 cm1 ouf ocp 0 ocm 0 a0
108/268 - multifunction timer (mft) multifunction timer (contd) interrupt/dma mask register (idmr) r255 - read/write register page: 10 reset value: 0000 0000 (00h) bit 7 = gtien : global timer interrupt enable . this bit is set and cleared by software. 0: disable all timer interrupts 1: enable all timer timer interrupts from enabled sources bit 6 = cp0d : capture 0 dma mask. this bit is set by software to enable a capt0 dma transfer and cleared by hardware at the end of the block transfer. 0: disable capture on reg0r dma 1: enable capture on reg0r dma bit 5 = cp0i : capture 0 interrupt mask . 0: disable capture on reg0r interrupt 1: enable capture on reg0r interrupt (or capt0 dma end of block interrupt if cp0d=1) bit 4 = cp1i : capture 1 interrupt mask . this bit is set and cleared by software. 0: disable capture on reg1r interrupt 1: enable capture on reg1r interrupt bit 3 = cm0d : compare 0 dma mask. this bit is set by software to enable a comp0 dma transfer and cleared by hardware at the end of the block transfer. 0: disable compare on cmp0r dma 1: enable compare on cmp0r dma bit 2 = cm0i : compare 0 interrupt mask . this bit is set and cleared by software. 0: disable compare on cmp0r interrupt 1: enable compare on cmp0r interrupt (or comp0 dma end of block interrupt if cm0d=1) bit 1 = cm1i : compare 1 interrupt mask . this bit is set and cleared by software. 0: disable compare on cmp1r interrupt 1: enable compare on cmp1r interrupt bit 0 = oui : overflow/underflow interrupt mask . this bit is set and cleared by software. 0: disable overflow/underflow interrupt 1: enable overflow/underflow interrupt dma counter pointer register (dcpr) r240 - read/write register page: 9 reset value: undefined bits 7:2 = dcp[7:2] : msbs of dma counter regis- ter address. these are the most significant bits of the dma counter register address programmable by soft- ware. the dcp2 bit may also be toggled by hard- ware if the timer dma section for the compare 0 channel is configured in swap mode. bit 1 = dma-srce : dma source selection. this bit is set and cleared by hardware. 0: dma source is a capture on reg0r register 1: dma destination is a compare on cmp0r reg- ister bit 0 = reg/mem : dma area selection . this bit is set and cleared by software. it selects the source and destination of the dma area 0: dma from/to memory 1: dma from/to register file 70 gt- ien cp0d cp0i cp1i cm0 d cm0i cm1i oui 70 dcp7 dcp6 dcp5 dcp4 dcp3 dcp2 dma srce reg/ mem
109/268 - multifunction timer (mft) multifunction timer (contd) dma address pointer register (dapr) r241 - read/write register page: 9 reset value: undefined bits 7:2 = dap[7:2] : msb of dma address regis- ter location. these are the most significant bits of the dma ad- dress register location programmable by software. the dap2 bit may also be toggled by hardware if the timer dma section for the compare 0 channel is configured in swap mode. note: during a dma transfer with the register file, the dapr is not used; however, in swap mode, dap2 is used to point to the correct table. bit 1 = dma-srce : dma source selection. this bit is fixed by hardware. 0: dma source is a capture on reg0r register 1: dma destination is a compare on the cmp0r register bit 0 = prg/dat: dma memory selection . this bit is set and cleared by software. it is only meaningful if dcpr.reg/mem=0. 0: the isr register is used to extend the address of data transferred by dma (see mmu chapter). 1: the dmasr register is used to extend the ad- dress of data transferred by dma (see mmu chapter). interrupt vector register (t_ivr) r242 - read/write register page: 9 reset value: xxxx xxx0 this register is used as a vector, pointing to the 16-bit interrupt vectors in memory which contain the starting addresses of the three interrupt sub- routines managed by each timer. only one interrupt vector register is available for each timer, and it is able to manage three interrupt groups, because the 3 least significant bits are fixed by hardware depending on the group which generated the interrupt request. in order to determine which request generated the interrupt within a group, the t_flagr register can be used to check the relevant interrupt source. bits 7:3 = v[4:0]: msb of the vector address. these bits are user programmable and contain the five most significant bits of the timer interrupt vec- tor addresses in memory. in any case, an 8-bit ad- dress can be used to indicate the timer interrupt vector locations, because they are within the first 256 memory locations (see interrupt and dma chapters). bits 2:1 = w[1:0]: vector address bits. these bits are equivalent to bit 1 and bit 2 of the timer interrupt vector addresses in memory. they are fixed by hardware, depending on the group of sources which generated the interrupt request as follows:. bit 0 = this bit is forced by hardware to 0. 70 dap 7 dap 6 dap5 dap4 dap3 dap2 dma srce prg /dat reg/mem prg/dat dma source/destination 0 0 1 1 0 1 0 1 isr register used to address memory dmasr register used to address memory register file register file 70 v4 v3 v2 v1 v0 w1 w0 0 w1 w0 interrupt source 0 0 1 1 0 1 0 1 overflow/underflow even interrupt not available capture event interrupt compare event interrupt
110/268 - multifunction timer (mft) multifunction timer (contd) interrupt/dma control register (idcr) r243 - read/write register page: 9 reset value: 1100 0111 (c7h) bit 7 = cpe : capture 0 eob . this bit is set by hardware when the end of block condition is reached during a capture 0 dma op- eration with the swap mode enabled. when swap mode is disabled (swen bit = 0), the cpe bit is forced to 1 by hardware. 0: no end of block condition 1: capture 0 end of block bit 6 = cme : compare 0 eob . this bit is set by hardware when the end of block condition is reached during a compare 0 dma op- eration with the swap mode enabled. when the swap mode is disabled (swen bit = 0), the cme bit is forced to 1 by hardware. 0: no end of block condition 1: compare 0 end of block bit 5 = dcts : dma capture transfer source . this bit is set and cleared by software. it selects the source of the dma operation related to the channel associated with the capture 0. note: the i/o port source is available only on spe- cific devices. 0: reg0r register 1: i/o port. bit 4 = dctd : dma compare transfer destination . this bit is set and cleared by software. it selects the destination of the dma operation related to the channel associated with compare 0. note: the i/o port destination is available only on specific devices. 0: cmp0r register 1: i/o port bit 3 = swen : swap function enable . this bit is set and cleared by software. 0: disable swap mode 1: enable swap mode for both dma channels. bits 2:0 = pl[2:0]: interrupt/dma priority level . with these three bits it is possible to select the in- terrupt and dma priority level of each timer, as one of eight levels (see interrupt/dma chapter). i/o connection register (iocr) r248 - read/write register page: 9 reset value: 1111 1100 (fch) bits 7:2 = not used. bit 1 = sc1 : select connection odd. this bit is set and cleared by software. it selects if the txouta and txina pins for timer 1 and timer 3 are connected on-chip or not. 0: t1outa / t1ina and t3outa/ t3ina uncon- nected 1: t1outa connected internally to t1ina and t3outa connected internally to t3ina bit 0 = sc0 : select connection even. this bit is set and cleared by software. it selects if the txouta and txina pins for timer 0 and timer 2 are connected on-chip or not. 0: t0outa / t0ina and t2outa/ t2ina uncon- nected 1: t0outa connected internally to t0ina and t2outa connected internally to t2ina note: timer 1 and 2 are available only on some devices. refer to the device block diagram and register map. 70 cpe cme dcts dct d swe n pl2 pl1 pl0 70 sc1 sc0
111/268 - osdram controller 8.4 osdram controller 8.4.1 introduction the osdram controller handles the interface be- tween the display controller, the cpu and the os- dram. the time slots are allocated to each unit in order to optimize the response time. the main features of the osdram controller are the following: n memory mapped in memory space (segment 22h of the mmu) n dma access for display control n direct cpu access 8.4.2 functional description the osdram controller manages the data flows between the different sub-units (display controller, cpu) and the osdram. a specific set of buses (16-bit data, 9-bit addresses) is dedicated to these data flows. the osdram controller accesses these buses in real time. the osdram controller has registers mapped in the st9 register file. as this osdram controller has also to deal with tv real time signals (on-screen-display), a spe- cific controller manages all exchanges: C its timing generator uses the same frequency generator as the display (pixel frequency multi- plier), C its controller can work in two tv modes: C single mode : all time slots are dedicated to the cpu. C shared mode : time slots are shared between the cpu and the display. the shared mode is controlled by the display controller. C its architecture gives priority to the tv real time constraints: whenever there is access contention between the cpu and the display (shared mode), the cpu is automatically forced in a wait configuration until its request is served. C its controller enables a third operating mode (stand-alone mode) which allows the application to access the osdram while the display is turned off. in this case, the osdram controller uses the cpu main clock. figure 50. display architecture overview 4 * 3 bits display controller osdram controller osd display ram cpu interface rom font matrix register buses memory buses address (6+4 bits) osd address (9 bits) osd data (16 bits) rgb fb translucency tslu data (8 bits) address (22 bits) data (8 bits)
112/268 - osdram controller osdram controller (contd) 8.4.2.1 time sharing during display the time necessary to display a character on the screen defines the basic repetitive cycle of the os- dram controller. this whole cycle represents therefore 18 clock periods. this cycle is divided in 9 sub-cycles called slots. each slot is allocated in real-time either to the cpu or the display: C in single mode, this 9-slot cycle is repeated con- tinuously providing only cpu slots (single cycle), until the osdram controller is switched off by the main program execution. C in shared mode, this 9-slot cycle provides dis- play slots followed by cpu slots. each slot represents a two-byte exchange (read or write) between the osdram memory and the oth- er units: display reading slot (dis): 16 bits are read from the osdram and sent to the display unit, the ad- dress being defined by the display address gener- ator. direct cpu access slot (cpu): 16 bits are ex- changed (read or write) between the osdram and its controller but only 8 bits are exchanged with the cpu, the address being defined by the cpu memory address bus. figure 51. time sharing during display display reading is handled as follows: C dis(1) & dis(2) are dedicated to reading the character code, its parallel attributes & associat- ed palette pointer. C dis(3) provides the foreground palette. C dis(4) provides the background palette. in case of underline activation (refer to the osd control- ler paragraph for more details), the dis(4) slot is no longer provides the background palette con- tent (useless information) but recovers the un- derline color set data. the cpu write accesses are handled as follows: because of the 16-bit word width inside the os- dram matrix, it is obviously necessary to perform a cpu write access in 2 steps: C reading the osdram word C rewriting it with the same values except for the 8 modified bits. each time a cpu write operation is started, the next following cpu slot will be used as a read slot, the effective write to the osdram being complet- ed at the next cpu slot. 8.4.2.2 time sharing within the tv line at the beginning of each tv line, the osdram is accessed (read) by the display controller in order to get all the row attributes. when the tv line is recognized as the one where data have to be dis- played, the shared cycle is activated at the time the data has to be processed for display. cpu (r/w) cpu (r/w) cpu (r/w) cpu (r/w) cpu (r/w) cpu (r/w) cpu (r/w) cpu (r/w) cpu (r/w) cpu (r/w) dis (1) cpu (r/w) dis (2) cpu (r/w) dis (3) cpu (r/w) dis (4) cpu (r/w) shared cycle single cycle one character display time
113/268 - osdram controller osdram controller (contd) 8.4.3 osdram controller reset configuration during and after a reset, the osdram access is disabled. when the osdram controller is software disa- bled, it will: 1. complete the current slot. 2. complete any pending write operation (a few slots may elapse). 3. switch off any osdram interface activity. 8.4.3.1 osdram controller running modes 2 control bits called osde (osd enable) and dion (display on) are used to enable the os- dram controller. both are also shared by the dis- play controller. these 2 bits are located in the osder register. this register is described in the on screen display controller chapter. 8.4.3.2 cpu slowdown on osdram access as described above, the osdram controller puts priority on tv real time constraints and may slow- down the cpu (through wait cycle insertion) when any osdram access is requested. the ef- fective duration of the cpu slowdown is a complex function of the osdram controller working mode and of the respective pixclk frequency (os- dram frequency) and the core intclk frequen- cy. 8.4.3.3 osdram mapping the osdram is mapped in the memory space, segment 22h, starting from address 0000h to ad- dress 017fh (384 bytes). the osdram mapping is described in the on screen display controller chapter.
114/268 - on screen display controller (osd) 8.5 on screen display controller (osd) 8.5.1 introduction the osd displays closed captioning (eia708 specification) or other character data and menus on a tv screen. each row can be defined through three different display configurations: C serial mode: each character is defined by an 8- bit word which provides the character address into the font rom memory. some codes are re- served for color controls and do not address any character description. they are displayed as spaces and as a direct consequence are active on a word basis. this mode fully supports the closed captioning format. C basic parallel mode: each character is defined by a 16-bit word which provides the character ad- dress in the font rom memory and its color at- tribute. this mode is called parallel as the colors are definable on a per character basis. C extended parallel mode: each character is de- fined by a 24-bit word which provides the charac- ter address in the font rom memory and its color and shape attributes. this mode is called parallel as the attributes are definable on a per character basis. 8.5.2 general features n 50/60 hz and 100/120 hz* operation n 525/625 lines operation, 4/3 or 16/9 format n interlaced or progressive scanning n 18x26 or 9x13 character matrix user definable in rom. both matrixes can be mixed. n up to 63 characters per row n 7 character sizes in 18x26, 4 in 9x13 n 512 possible colors in 4x16-entry palettes n 8 levels of translucency on fast blanking n serial character mode supporting closed captioning format n basic parallel mode for character based color definition n extended parallel mode for character based color and shape definition n mouse pointer (user definable in rom) n rounding, fringing, shadowing, flashing, scrolling, italics, and various underlining modes definition of terms used in this chapter C pixel : minimum displayed element that the dis- play controller can handle. its vertical physical size is always one tv line. its horizontal physical size is directly linked to the basic clock frequency (called pixel clock) which synchronizes the osd and is therefore independent of any magnifica- tion factor which may be applied to the displayed element. C dot : a dot defines the displayed element which corresponds to a single bit read from the font rom memory. a dot is represented on the screen by a "matrix" of pixels. the matrix size de- pends on the magnification factor applied. 8.5.3 functional description all characters are user definable by masking the font rom content (except the one corresponding to code 00h which is reserved for test). two differ- ent matrixes can be used and mixed: C 18x26 character matrix C 9x13 character matrix the hardware display system has the capability of displaying one character row and requires the cpu to update the next display buffer prior to dis- playing the next row. using a real time routine, the on screen display supports the display of as many character rows as the tv screen can physi- cally handle. the osd can display up to 63 characters per row, depending on the row ram buffer size (user defin- able, see section 8.5.5.1 ). the osd is also designed to handle a mouse pointer (see section 8.5.7 ). a smart pixel processing unit provides extended features such as rounding, fringe, or shadowing for better picture quality. other smart function such as flashing, scrolling, italics, underlining and mouse pointer allow the designing of a high quality display application. the screen insertion of the displayed characters is fully synchronized by the vertical and horizontal tv synchronizing signals. the osd controller generates the red, green, blue and fast blanking video signals through 8-level dac outputs. the fast blanking video signal can also be generated as a digital signal if needed. *available on some devices
115/268 - on screen display controller (osd) osd controller (contd) 8.5.3.1 display attributes n global screen attributes: C border color C border translucency C turn all background color into border color n row parameters and attributes: C row mode control (serial, basic parallel, extend- ed parallel) C row character count C horizontal and vertical shift C active range (used for vertical scrolling) C font matrix selection C size control (dot height and width definition) C flashing control C rounding control C fringe control n serial character attributes: C background color (16 user definable colors) C foreground color (16 user definable colors) C flashing control C italics control n palette parallel character attributes: C background color (16 user definable colors) C foreground color (16 user definable colors) n shape parallel character attributes: C character code extension C double height C double width C foreground palette extension (32 user definable colors) C background palette extension (32 user definable colors) C flashing control C shadowing control C fringe control n mouse pointer attributes: C fringe control C rounding control C foreground color (32 user definable colors) C double size C horizontal and vertical position 8.5.3.2 osd area when the display controller is turned on, the tv screen will show a specific color prior to any data display which is called the border color. the ef- fective border color is fully software programmable from a palette of 512 colors through 2 control reg- isters. the border area translucency can be chosen from 8 different levels, from fully transparent to fully opaque. the 3 translucency control bits are acces- sible through the border color control registers. when data are displayed by the osd, they form rows of characters. all characters of one row are horizontally aligned. for each displayed character, two kinds of colors must be programmed which are defined as: C background color C foreground color figure 52. osd area description 8.5.3.3 color processing further color elements may be generated by the display controller as a result of real time pixel cal- culations (they are not stored in the font rom memory). these are: C rounding pixels: they must be considered as calculated foreground pixels. C fringe pixels: they are always displayed with a black color and are never translucent. C underline pixels: they must be considered as calculated pixels. their colors are defined through independent underline color values. translucency levels are also programmable for underline pixels. a border color 1 character row 1 displayed character background color foreground color area a
116/268 - on screen display controller (osd) osd controller (contd) all colors are taken from a double palette set (background and foreground) which are both os- dram mapped and thus definable in real-time. the priority of all color layers is, from highest to lowest: mouse, underline, foreground & rounding, fringe, background and border. character code 00h is a test character and has no user customized content. it is always displayed with a border color and will appear as a non-dis- played character. 8.5.3.4 character matrix definition a character is described by a matrix of dots stored in the font rom memory. two matrix sizes are can be used to define each character pattern: ei- ther a 9x13 matrix or a 18x26 matrix. the matrix size can be redefined for each row display buffer; mixing the 2 matrix sizes on a same screen is therefore possible. refer to figure 61 , for an example of the font rom content. the 9x13 matrix is a compressed format where each bit represents a 2x2 pixel dot (with no magni- fication applied). in interlaced mode, for each dot, 2 pixels are generated on a field, the 2 others on the other field; each row of the matrix is used for both fields. the 18x26 matrix is an expanded format where each bit represents a 1x1 pixel dot (if no magnifi- cation). in interlaced mode, if no magnification is applied, each odd row of the matrix is displayed on a field, each even row on the other field. warning: as a result, when displaying the 18x26 matrix with no vertical magnification and in interlaced mode, flicker may be visible on charac- ters containing long single-pixel rows. to avoid this effect, either use double pixel horizontal lines, if possible, when designing the font (see figure 53 ). alternatively, use the double height attribute or choose the foreground and background colors for reduced contrast. figure 53. avoiding flicker on unmagnified 18x26 characters modified character design with visible flicker original character design
117/268 - on screen display controller (osd) osd controller (contd) 8.5.3.5 cursor & flash a cursor facility may be emulated under software control, using the flash attribute. this allows to have a flash-on-word in serial mode or a flash- on-character in extended parallel mode. the cursor facility first requires activating the flash on row control bit (refer to section 8.5.8.3 ), which acts as a general flash enable. then program the characters with flashing char- acter attribute(s) (serial or extended parallel) at the required locations. the flash effect is obtained by toggling the general flash enable bit. several flashing words or characters per screen can easily be implemented. 8.5.3.6 italic mode the italics attribute is a serial attribute; this means that italic mode is available in serial mode only. in the matrix description that follows, line 1 is at the top of the character, line 13 (or line 26) is at the bottom. the codes (seen as spaces) needed to activate and deactivate the italic attribute provide a con- venient method for solving border problems be- tween italic and non-italic characters. figure 54. italic character mode 18x26 26 1 21 20 17 16 13 12 9 8 5 4 9x13 shift row shift 5 4 3 2 1 0 2.5 2 1.5 1 0.5 0 normal italic 13 1 11 10 9 8 7 6 5 4 3 2 dot row dot
118/268 - on screen display controller (osd) osd controller (contd) if the italic attribute is still active at the end of the row, the last character code to be displayed is truncated to the vertical position where it would have finished without the italic attribute. if the background color is changed while italics are enabled, then the color attribute (seen as a space) is not slanted. the right edge background corresponding to a control character is never slanted. when a background code follows an italic charac- ter, then the background color of the italic charac- ter extends half way into the displayed background code location, regardless of the background pal- ette m bit (refer to section 8.5.6.4 for a description of the m bit). in the case where a background code is followed by a second background code while italics are on, the first background color will extend half way into the second background location. the edges of the 00h code (test character seen as a border color) are never slanted. the right edge of the 00h code is never slanted. when a 00h code follows an italic character, then the background color of the italic character ex- tends half way into the 00h code location. in case a 00h code is followed by a background code while italics are on, the 00h code is never ex- tended into the following code location. 8.5.3.7 rounding and fringe rounding can be enabled or disabled row by row (see section 8.5.8.3 ). for a 18x26 matrix size, there is no rounding facil- ity when the character size is (1x,1y). for any other (x,y) size combinations, the round- ing facility is allowed for the 18x26 font matrix, and rounding is available in any of the 3 row modes (serial, basic parallel, extended parallel). the fringe mechanism can be enabled or disabled row by row (see row attributes description), but it can also be defined on a character basis in ex- tended parallel mode (see shape parallel at- tributes for more details). the fringe mechanism can be activated for any size and both matrix formats. please note that, for both matrixes, in the case of fringe usage in 1y vertical size and interlaced mode, a flicker may appear on the screen as the fringe information is built on a field basis. figure 55. rounding and fringe foreground dot size rounding dot size fringe dot size 9 x13 18 x 26 drawing conventions: partial details rounding and fringe in size (2x,2y) for 18x26 rounding and fringe (9x13 matrix only) partial details (9x13 matrix only) rounding and fringe partial details 9x13 matrix 18x26 matrix rounding and fringe in size (1x,1y) in size (1.5x,2y) in size (1.5x,1y) rounding and fringe in size (4x,4y) for 18x26
119/268 - on screen display controller (osd) osd controller (contd) 8.5.3.8 scrolling the row ram buffer architecture of the display al- lows all scrolling operations to be performed very easily by software: scroll up, scroll down, scroll left, scroll right and any horizontal/vertical mix. in addition to the character row scrolling, a vertical smooth scrolling has been implemented. it re- quires defining the active range for each dis- played row (refer to section 8.5.8.4 ). 8.5.3.9 color palettes the display controller provides 4 user-definable palettes: two 16-color foreground palettes (one ba- sic and one extended), and two 16-color back- ground palettes (one basic and one extended). each color is defined using 16 bits: C foreground palette: 3 bits for red level, 3 bits for green level, 3 bits for blue level, 3 bits for translucency, and 3 bits for the underline mode control. C background palette: 3 bits for red level, 3 bits for green level, 3 bits for blue level, 3 bits for translucency, and 1 bit for immediate color change control. two palettes are always available (one foreground palette and one background palette). the 2 other palettes are only accessible in extended parallel mode. the palettes available in serial and basic parallel modes depend on the value of the pasw bit in the osddr register. 8.5.3.10 underline mode control the osd is able to underline any character of the 9x13 or 18x26 matrix with 3 different colors select- ed from a palette, and 2 different dot lines. using 3 bits (see the color palettes paragraph above), it is possible to define the underline mode associated with each foreground palette entry. in 9x13 mode, single or double underline can be set on lines 12 and 13 with the foreground color or two specific colors defined in underline color sets 1 & 2. in 18x26 mode, single or double underline can be set on lines 23-24 and 25-26 with the foreground color or two specific colors defined in underline color sets 1 & 2. for more details please refer to section 8.5.6 .
120/268 - on screen display controller (osd) osd controller (contd) 8.5.3.11 translucency function the translucency feature is designed to provide a better osd quality while displaying rows in mixed mode. instead of forcing the background color of any character to any full intensity color, (which will pre- vent the viewer from seeing a significant amount of the video picture), or having a fully transparent background (i.e. no background) which makes the osd more difficult to read for the viewer, the trans- lucency provides a real time mix between both the video and the osd background information. this feature will appear as a boxing effect around all the displayed characters. the translucency can be handled in two different ways at application level, depending on the video processor used in the application. 1. when the video processor accepts an analog control of the fast switch osd signal (called fb), the translucency can be handled directly through the real time amplitude of the fb signal (refer to color attribute control for border, back- ground palette and underline color settings). 2. when the video processor accepts only a digital fb signal, the translucency function may be im- plemented on the chassis with the help of an additional digital output of the mcu, which is provided as an i/o pin alternate function. this digital output called tslu is active (set to 1) when the osd displays the background and foreground or when the mute is active (refer to the description of the lsm[2:0] bits in the osdmr reg- ister) and is inactive the rest of the time (during foreground or if no display), including character 00h. this tslu signal is controlled by the tsle bit in the osder register. when not used, (tsle=0), the tslu signal is held at 1 by hardware. application note in order to enable the translucency function (see example no. 2, above), the following procedure must be performed: C fast blanking must be set to digital mode. set bit difb (bit 7) of register osdbcr1 (r247, page 42) to 1. refer to section 8.5.9 register descrip- tion . C initialize port 3.0 as a push-pull type alternate function output. refer to section 8.5.3 function- al description . C set bit tsle (bit 2) of register osder (r248, page 42) to 1. refer to section 8.5.9 register description . C for the selected colors (i.e. those which will ap- pear as transparent with contrast reduction), set bits bt[2:0] to 0. refer to section 8.5.6.4 back- ground palettes . figure 56. digital translucency output pin example a current displayed video line tlsu digital output fb (active high) no display foreground no display transparent background
121/268 - on screen display controller (osd) osd controller (contd) figure 57. digital translucency display scheme using stv2238d in pqfp64 package figure 58. application example using stv224x/228x in sdip56 package video processor (stv2238d) contrast reduction internal red internal green internal blue rout gout bout rgb switch st9 mcu tslu r g fb b stv224x/228x chroma processor 2.2 k w 1.5 k w 1 k w 2.7 k w tslu fb fb osd st9 mcu
122/268 - on screen display controller (osd) 8.5.3.12 mouse pointer the mouse pointer icon is built as an 18x26 dot matrix; it is fully user definable, selected from any of the osd characters in font rom memory (ex- cept 00h). this allows a multiple mouse configura- tion. the mouse pointer dots are processed like any 9x13 character, i.e. any dot is displayed on both fields and represents a final 2x2 pixel area on the screen. the mouse pointer represents a 18x26 character displayed in 2y-2x size. only the mouse pointer foreground is displayed. the mouse pointer background is transparent. the mouse pointer dot processing includes the standard foreground pixel processing and also the rounding and fringe. the algorithms used are the same as for characters (for more details, refer to the rounding and fringe section above, assuming a 9x13 character matrix case extended to an 18x26 matrix). the mouse pointer uses one of the foreground palette entries to define its pixel color. all features of the foreground palette are retained except the underline. the priority of all color layers is from highest-to- lowest: mouse foreground, mouse fringe, osd characters and border. 8.5.4 horizontal and vertical sync 8.5.4.1 pixel clock control the pixel clock is issued from a frequency multipli- er which is locked to the main crystal frequency. the synthesized frequency is software program- mable (4-bit value defining the multiplying factor) which provides flexibility for supporting various ap- plication conditions, from a basic 4/3 screen for- mat and a 1h horizontal sweep to a 16/9 format with a 2h sweep, interlaced or progressive scan- ning. for more information, refer to the timing and clock controller chapter. note: it is recommended to wait for a stable clock (approx. 35 ms) from the frequency multiplier be- fore enabling the osdram controller.
123/268 - on screen display controller (osd) osd controller (contd) vertical & horizontal sync pulse inputs a spike filter has been implemented on the vertical sync input. this circuit is inserted after internal po- larity compensation of the vsync input signal (see vpol bit of the delay register, osddr). it masks any spike on the vertical sync pulse with a duration smaller than 3s. the leading edge of the vsync pin is affected by the vertical sync pulse cleaner. the vsync edges are internally delayed by 3s. a schmitt trigger provides noise immunity on the horizontal sync pulse input and will add a delay between the deflection pulse and the effective count start of the osd line processing. 8.5.4.2 field detection in interlaced mode for tv sets working in interlaced mode, the dis- play controller has to retrieve the field information (some pixel information, like 18x26 matrix charac- ters, rounding or fringe, is field based). the display is synchronized to hsync and vsync inputs. the phase relationship of these signals may be different from one chassis type to another. therefore, in order to prevent vertical osd jitter, some circuitry is implemented to pro- vide a stable and secure field detection (osd jitter may appear if the rising edge of an external verti- cal sync pulse coincides with that of an external horizontal sync pulse). this circuitry delays the vertical sync leading edge internally. the delay ap- plied is software programmable through a 4-bit value (refer to bit dbls in the osddr register). the field information is then extracted by appropri- ate hardware logic. 8.5.4.3 display behaviour in 2h modes the 2h mode corresponds to a double scan dis- play mode: the line frequency is doubled (to 31.5 khz) compared to the traditional 60 hz field, 262.5 lines per field. this mode requires doubling the pixel frequency and also adjusting some timing op- erations (refer to section 8.5.4.1 and section 8.5.4.2 ). this feature is controlled by the dbls bit in the osder register. the double scan may be used in interlaced mode (100/120 hz field frequency) or in progressive scanning (non-interlaced mode, 50/60 hz field frequency). this feature is enabled by the nids bit in the os- der register. rgb-fb line start mute the r, g, b & fb outputs are muted after each horizontal sync pulse received on the hsync pin. the mute duration is controlled by software through a 3-bit value; these bits are called lsm(2:0) and are located in the mute register osdmr. when the display works in 1h mode (bit dbls re- set), the mute duration can be adjusted in 2s steps from 2 to 14 s. when the display works in 2h mode (bit dbls set), the mute duration can be adjusted in 1s steps from 1 to 7 s. when the 3-bit mute value is zero, the r, g, b & fb display outputs are muted during the duration of the horizontal sync pulse received on the hsync pin. for more details, refer to the dbls bit in the os- der and the lsm bits in the osdmr register. the hsy bit in the osdfbr register provides an image of the mute.
124/268 - on screen display controller (osd) osd controller (contd) 8.5.5 programming the display the row-wise ram buffer contains the description of the characters to display: C row and character attributes (color, shape etc.) C horizontal shift code C character codes (addressing the font rom) while one row buffer is displayed on the screen, the cpu has time to prepare the content of the next character row by filling up the second row buffer. at the time the next row must be displayed, the display controller will point to the second row buffer, allowing the cpu to start loading data into the first row buffer for the following row. an inter- rupt request is generated each time the buffer pointer toggles. note: the display and the mouse share the same interrupt line. in configurations with mouse, the dint and moint bits in the osdfbr register can be used to determine the interrupt cause. the vertical location of the next character row on the screen is programmed by software through the event line value (refer to figure 65 ). the vertical position of the beam is memorized by the line counter which counts the tv horizontal synchroni- zation pulses (called here "scan line"). when the scan line counter matches the event line value the buffer toggle mechanism is activated. 8.5.5.1 osdram mapping the osdram is mapped in segment 22h of the memory space. in addition to row buffers, it is used to store color palettes and information concerning mouse point- er. note: the reset value of the osdram contents is undefined. general overview the figure 59 gives a general overview of the os- dram mapping.
125/268 - on screen display controller (osd) osd controller (contd) figure 59. osdram mapping 2n+b 2n 2p+a 2p row buffer 1 row buffer 2 8fh 00h buffer address, mouse & description section a & b values depend on the row mode and on the number of characters to display in the row segment 22h 0fh 0eh 0dh 0ch 0bh 0ah 09h 08h 07h 06h 05h 04h 03h 02h 01h 00h free for user free for user mouse pointer horizontal position (low) mouse pointer horizontal position (high) mouse pointer vertical position (low) mouse pointer vertical position (high) mouse font code (low) mouse font code (high) + foreground color underline color set 2 (low) underline color set 2 (high) underline color set 1 (low) underline color set 1 (high) first buffer start address (low) first buffer start address (high) event line (low) event line (high) 8fh 70h 6fh 50h 4fh 30h 2fh 10h extended background palette extended foreground palette basic foreground palette basic background palette 2p+3 2p+2 2p+1 2p active range row attributes horizontal shift (low) horizontal shift (high) + row char. count next buffer start addr. (low) next buffer start addr. (high) + row mode 2p+6 char (serial mode) 2p+4 2p+5 . . . . char + palette attrib. (basic parallel mode) char + palette attrib. + shape attrib. (extended parallel mode) osdram general features 00h to 4f, 6fh or 8fh depending on color palettes configured row buffer any even address between 50h and 1feh palette 2p is the start address of the first row buffer notes: active range
126/268 - on screen display controller (osd) osd controller (contd) 8.5.5.2 row buffer description the start address for each buffer must be even. starting from address 2p+6, write a string corre- sponding to the character codes and the possible attributes as in the example below: 8.5.5.3 osdram mapping example 1 the left column of figure 60 gives an example of osdram mapping for the following configuration: C the display uses basic parallel mode C only the two basic color palettes are used C 36 characters are displayed per row C the first buffer start address (to be stored in 0002h and 0003h) is 0050h C the next buffer start address to be stored in buffer 1 (address 0050h and 0051h) is 409eh (009eh is the address of buffer 2, and 40h is the code for basic parallel mode. refer to section 8.5.8.1 ). C the next buffer start address to be stored in buffer 2 (address 009eh and 009fh) is 4050h (0050h is the address of buffer 1, and 40h is the code for basic parallel mode. refer to section 8.5.8.1 for more details). 8.5.5.4 osdram mapping example 2 the right column of figure 60 gives an example of osdram mapping for the following configuration: C the display uses extended parallel mode C the four color palettes are used C 36 characters are displayed per row C the first buffer start address (to be stored in 0002h and 0003h) is 0090h C the next buffer start address to be stored in buffer 1 (address 0090h and 0091h) is 8102h (0102h is the address of buffer 2, and 80h is the code for extended parallel mode. refer to sec- tion 8.5.8.1 for more details). C the next buffer start address to be stored in buffer 2 (address 0102h and 0103h) is 8090h (0090h is the address of buffer 1, and 80h is the code for extended parallel mode. refer to sec- tion 8.5.8.1 for more details). note: to keep some osdram locations free, configure only those features that you really use (color palettes, underline palettes and mouse pointer data), as shown in the two examples. byte serial mode basic parallel mode extended parallel mode 1 char or attrib1 char1 char1 2 char or attrib2 paletteattrib1 paletteattrib1 3 char or attrib3 char2 shapeattrib1 4 char or attrib4 paletteattrib2 char2 5 char or attrib5 char3 paletteattrib2 6 char or attrib6 paletteattrib3 shapeattrib2 ... ... ... ...
127/268 - on screen display controller (osd) figure 60. parallel mode mapping examples 17fh 0fh 0eh 0dh 0ch 0bh 0ah 09h 08h 07h 06h 05h 04h 03h 02h 01h 00h free for user mouse pointer horizontal position (low) mouse pointer horizontal position (high) mouse pointer vertical position (low) mouse pointer vertical position (high) mouse coding data (low) mouse coding data (high) + foreground color underline color set 2 (low) underline color set 2 (high) underline color set 1 (low) underline color set 1 (high) first buffer start address (low) first buffer start address (high) event line (low) event line (high) 4fh 30h 2fh 10h basic foreground palette basic background palette 56h 57h 58h 59h character code 1 character code 2 palette attribute 1 9ch 9dh character code 36 palette attribute 36 53h 52h 51h 50h active range row attributes horizontal shift (low) horizontal shift (high) + row char. count next buffer start addr. (low) next buffer start addr. (high) + row mode 54h 55h a4h a5h a6h a7h character code 1 palette attribute 2 palette attribute 1 character code 2 eah ebh character code 36 palette attribute 36 a1h a0h 9fh 9eh active range row attributes horizontal shift (low) horizontal shift (high) + row char. number next buffer start addr. (low) next buffer start addr. (high) + row mode a2h a3h free for user ech palette attribute 2 17fh 0fh 0eh 0dh 0ch 0bh 0ah 09h 08h 07h 06h 05h 04h 03h 02h 01h 00h mouse pointer horizontal position (low) mouse pointer horizontal position (high) mouse pointer vertical position (low) mouse pointer vertical position (high) mouse coding data (low) mouse coding data (high) + foreground color underline color set 2 (low) underline color set 2 (high) underline color set 1 (low) underline color set 1 (high) first buffer start address (low) first buffer start address (high) event line (low) event line (high) 8fh 70h 6fh 50h 4fh 30h 2fh 10h extended background palette extended foreground palette basic foreground palette basic background palette 96h 97h 98h 99h character code 1 character code 2 palette attribute 1 shape attribute 1 ffh 100h 101h character code 36 palette attribute 36 shape attribute 36 93h 92h 91h 90h active range row attributes horizontal shift (low) horizontal shift (high) + row char. count next buffer start addr. (low) next buffer start addr. (high) + row mode 94h 95h 108h 109h 10ah 10bh character code 1 character code 2 palette attribute 1 shape attribute 1 171h 172h 173h character code 36 palette attribute 36 shape attribute 36 105h 104h 103h 102h active range row attributes horizontal shift (low) horizontal shift (high) + row char. number next buffer start addr. (low) next buffer start addr. (high) + row mode 106h 107h free for user 174h second row buffer second row buffer first row buffer first row buffer basic parallel mode extended parallel mode free for user palettes palettes memory segment = 22h
128/268 - on screen display controller (osd) osd controller (contd) 8.5.5.5 font rom to address the characters in font rom refer to figure 61 . to obtain the character code, add the line code to the column code. example 1: the code for the a character is: example 2: the code for the { character is: note: the first two 9x13 characters (addresses 00h and 01h) are the control characters. they cannot be modified by the user. matrix line code + column code = character code 9x13 00h 41h 41h 18x26 60h 01h 61h matrix line code + column code = character code 9x13 82h 54h d6h 18x26 80h 1bh 9bh
129/268 - on screen display controller (osd) figure 61. st92196a font rom contents
130/268 - on screen display controller (osd) osd controller (contd) 8.5.5.6 event line address in segment 22h: 00h (bits 15:8), 01h (bits 7:0) el[8:0] is a 9-bit number specifying at which tv line number the character row display should start. for more details refer to section 8.5.8.8 bits 15:8: are at address 00h in segment 22h. bits 7:0 are at address 01h bits 15:9 are reserved. 8.5.5.7 first buffer start address address in segment 22h: 02h (bits 15:8), 03h (bits 7:0) to handle the display properly, the user must store the start address of the first osdram row buffer (the row buffer containing the first row to be dis- played when the display controller is turned on). two bytes are reserved for this in the osdram. (see figure 59 ). bits 15:8 are at address 02h in segment 22h bits 7:0 are at address 03h bits 15:9 are reserved. as row buffer start addresses are always even ad- dresses, bit 0 is forced to 0 by hardware. 15 8 7 0 - - - - - - - el8 el7 el6 el5 el4 el3 el2 el1 el0 15 8 7 0 - - - - - - - fsa8 fsa7 fsa6 fsa5 fsa4 fsa3 fsa2 fsa1 0
131/268 - on screen display controller (osd) osd controller (contd) 8.5.6 programming the color palettes the palette attributes are coded inside the two palettes (basic background and foreground, and extended background and foreground); they are therefore accessible in all modes, parallel as well as serial. a palette contains 16 colors each defined with a 16-bit word. for each color, you can define the red level (1 of 8 values), the green level (1 value among 8), the blue level (1 value among 8), and the translucency level (1 value among 8). the color palettes also bring improvements in un- derline control to allow for windows-like buttons. once programmed, color palettes can be changed in real-time when the osd is running, that is to say when the software is filling one row buffer while the other one is displayed (but take care that the row currently displayed may be using some of the colors which you want to modify).
132/268 - on screen display controller (osd) osd controller (contd) 8.5.6.1 underline color set 1 (usc1) address in segment 22h: 04h (bits 15:8), 05h (bits 7:0) to support windows-like button effects, the color of the 2 (or 4 in 18x26 matrix) bottom dot lines of a character row may be defined using the underline attributes. two dedicated 2-byte words define 2 color sets, underline color set 1 called ucs1 and underline color set 2 called ucs2. they are used by the underline mode in addition to the current foreground color. this provides a four color choice for both rows 12 and 13 (9x13 character matrix) or pair of rows 23- 24 and 25-26 (18x26 character matrix): none (background), foreground, ucs1 or ucs2, as shown in table 24 . the ucs1 data is mapped in a fixed osdram lo- cation (see figure 59 ). bits 15:12 = free for the user bits 11:9 = u1t[2:0] underline color set 1 translu- cency these bits configure the background translucency level applied to the color (refer to section 8.5.3.11 for more details). u1t[2:0] = 7 means that this color will be fully opaque (no video mixed in it on the display) u1t[2:0] = 0 means that this color will be fully transparent (the video is displayed instead of this color) bits 8:6 = u1r[2:0] underline color set 1 red color these bits configure the background red intensity for the color. u1r[2:0] = 0 means that no red is used to define the color. u1r[2:0] = 7 means that the maximum red intensi- ty is used in the color. bits 5:3 = u1g[2:0] underline color set 1 green color these bits configure the background green inten- sity for the color. u1g[2:0] = 0 means that no green is used to de- fine the color. u1g[2:0] = 7 means that the maximum green in- tensity is used in the color. bits 2:0 = u1b[2:0] underline color set 1 blue color these bits configure the background blue intensity for the color. u1b[2:0] = 0 means that no blue is used to define the color. u1b[2:0] = 7 means that the maximum blue inten- sity is used in the color. 15 8 7 0 u1t2 u1t1 u1t0 u1r2 u1r1 u1r0 u1g2 u1g1 u1g0 u1b2 u1b1 u1b0
133/268 - on screen display controller (osd) osd controller (contd) 8.5.6.2 underline color set 2 (ucs2) address in segment 22h: 06h (bits 15:8), 07h (bits 7:0) bits 15:12 = free for the user bits 11:9 = u2t[2:0] underline color set 1 translu- cency these bits configure the background translucency level applied to the color (refer to section 8.5.3.11 for more details). u2t[2:0] = 7 means that this color will be fully opaque (no video mixed in it on the display) u2t[2:0] = 0 means that this color will be fully transparent (the video is displayed instead of this color) bits 8:6 = u2r[2:0] underline color set 1 red color these bits configure the background red intensity for the color. u2r[2:0] = 0 means that no red is used to define the color. u2r[2:0] = 7 means that the maximum red intensi- ty is used in the color. bits 5:3 = u2g[2:0] underline color set 1 green color these bits configure the background green inten- sity for the color. u2g[2:0] = 0 means that no green is used to de- fine the color. u2g[2:0] = 7 means that the maximum green in- tensity is used in the color. bits 2:0 = u2b[2:0] underline color set 1 blue color these bits configure the background blue intensity for the color. u2b[2:0] = 0 means that no blue is used to define the color. u2b[2:0] = 7 means that the maximum blue inten- sity is used in the color. warning : the ucs1 and ucs2 data may be used as row attributes providing more than 3 underline colors on screen. this requires taking some care when their contents are modified. the ucs1 and ucs2 contents are fetched for dis- play only when dot lines 12/13 of the character are being processed, but at that time (while dot lines 12 and 13 are processed) any change to ucs1 or ucs2 is forbidden. software should change the ucs1 or ucs2 while the display processes character dot lines 1 to 11. it is recommended to associate the ucs1 or ucs2 management of the currently displayed buffer with the routine which handles the next buffer prepara- tion. refer to section 8.5.8.9 . 15 8 7 0 - - - - u2t2 u2t1 u2t0 u2r2 u2r1 u2r0 u2g2 u2g1 u2g0 u2b2 u2b1 u2b0
134/268 - on screen display controller (osd) osd controller (contd) 8.5.6.3 foreground palettes the foreground palettes (basic and extended) both use the same principle: C the basic foreground palette is stored in os- dram (segment 22h) starting from 10h to 2fh (see figure 59 ). C the extended foreground palette is stored in os- dram (segment 22h) starting from 50h to 6fh (see figure 59 ). a 16-bit word is used to define each color in the palette, located at even addresses between 10h and 2eh (even value) for the basic foreground pal- ette, and between 50h and 6eh (even value) for the extended foreground one. figure 62. basic foreground palette mapping bits 15 = free for the user bits 14:12 = u[2:0] underline mode control bits . these bits configure the underline mode for the dot line 12 (lines 23 and 24 if using the 18x26 ma- trix) and line 13 (lines 25 and 26 if using the 18x26 matrix). see table 24 . bits 11:9 = ft[2:0] foreground translucency these bits configure the foreground translucency level applied to the color (refer to section 8.5.3.11 for more details). ft[2:0] = 7 means that this color will be fully opaque (no video mixed in it on the display) ft[2:0] = 0 means that this color will be fully trans- parent (the video is displayed instead of this color) bits 8:6 = fr[2:0] foreground red color these bits configure the foreground red intensity for the color. fr[2:0] = 0 means that no red is used to define the color. fr[2:0] = 7 means that the maximum red intensity is used in the color. bits 5:3 = fg[2:0] foreground green color these bits configure the foreground green intensi- ty for the color. fg[2:0] = 0 means that no green is used to define the color. fg[2:0] = 7 means that the maximum green inten- sity is used in the color. bits 2:0 = fb[2:0] foreground blue color these bits configure the foreground blue intensity for the color. fb[2:0] = 0 means that no blue is used to define the color. fb[2:0] = 7 means that the maximum blue intensi- ty is used in the color. 15 8 7 0 u2 u1 u0 ft2 ft1 ft0 fr2 fr1 fr0 fg2 fg1 fg0 fb2 fb1 fb0 10h 2fh u[2:0] ft[2:0] fr2 fr[1:0] fg[2:0] fb[2:0] color 0 color 1 12h u[2:0] ft[2:0] fr2 fr[1:0] fg[2:0] fb[2:0] 14h color 15 u[2:0] ft[2:0] fr2 fr[1:0] fg[2:0] fb[2:0]
135/268 - on screen display controller (osd) osd controller (contd) table 24. underline mode control bits description note: take care when changing (or stopping) un- derline mode for a character, when the back- ground color is displayed with underline mode change in the center of the character (m bit in background palette). in this case, the underline doesnt stop at the end of the character but stops in the middle of the fol- lowing character. the underline color used is the last background color displayed in the current pixel line. this always happens, when changing underline mode in the following ways: C from thick to thin or no underline C from one thin color to another when the under- lining is not on the same line. (thick underline, in a 9 x 13 matrix, is underlining on 2 lines and, in a 18 x 26 matrix, on 4 lines. thin underline, in a 9 x 13 matrix, is underlining on 1 line and, in a 18 x 26 matrix, on 2 lines.) u2 u1 u0 underline color for a 9x13 dot matrix underline color for a 18x26 dot matrix 0 0 0 no underline no underline 0 0 1 line 12: foreground color lines 23-24: foreground color 0 1 0 line 13: underline color set 1 lines 25-26: underline color set 1 0 1 1 line 13: underline color set 2 lines 25-26: underline color set 2 1 0 0 line 12-13: underline color set 1 lines 23-24-25-26: underline color set 1 1 0 1 line 12-13: underline color set 2 lines 23-24-25-26: underline color set 2 110 line 12: underline color set 1; line 13: underline color set 2 lines 23-24: underline color set 1; lines 25-26: underline color set 2 111 line 12: underline color set 2; line 13: underline color set 1 lines 23-24: underline color set 2; lines 25-26: underline color set 1
136/268 - on screen display controller (osd) osd controller (contd) 8.5.6.4 background palettes the background palettes (basic and extended) both use the same principle: the basic background palette is stored in os- dram (segment 22h) starting from 30h to 4fh (see figure 59 ). the extended background palette is stored in os- dram (segment 22h) starting from 70h to 8fh (see figure 59 ). a 16-bit word is used to define each color in the palette, located at even addresses between 30h and 4eh (even value) for the basic background palette, and between 70h and 8eh (even value) for the extended background one. figure 63. basic background palette mapping bit 15 = m background color change bit . this bit determines where the background color change occurs. 0: the background color change takes effect im- mediately. 1: the background color change occurs in the center of the character. notes : C when the preceding character is slanted (italics on, only available in serial mode), a background color change only occurs in the center of the character regardless of the m bit value. C if the m bit is used in parallel mode at the begin- ning of a row, it is strongly recommended to in- sert a space or null character before setting the m bit in order to control the first half background color. bits 14:12 = free for the user bits 11:9 = bt[2:0] background translucency these bits configure the background translucency level applied to the color (refer to section 8.5.3.11 for more details). bt[2:0] = 7 means that this color will be fully opaque (no video mixed in it on the display) bt[2:0] = 0 means that this color will be fully trans- parent (the video is displayed instead of this color) bits 8:6 = br[2:0] background red color these bits configure the background red intensity for the color. br[2:0] = 0 means that no red is used to define the color. br[2:0] = 7 means that the maximum red intensity is used in the color. bits 5:3 = bg[2:0] background green color these bits configure the background green inten- sity for the color. bg[2:0] = 0 means that no green is used to define the color. bg[2:0] = 7 means that the maximum green inten- sity is used in the color. bits 2:0 = bb[2:0] background blue color these bits configure the background blue intensity for the color. bb[2:0] = 0 means that no blue is used to define the color. bb[2:0] = 7 means that the maximum blue intensi- ty is used in the color. 15 8 7 0 m bt2 bt1 bt0 br2 br1 br0 bg2 bg1 bg0 bb2 bb1 bb0 30h 4fh color 0 color 1 32h 34h color 15 m bt[2:0] br2 br[1:0] bg[2:0] bb[2:0] m bt[2:0] br2 m bt[2:0] br2 br[1:0] bg[2:0] bb[2:0] br[1:0] bg[2:0] bb[2:0]
137/268 - on screen display controller (osd) osd controller (contd) 8.5.7 programming the mouse pointer the mouse pointer is programmed using two con- trol bits stored in registers, and three 16-bit words located in osdram ( figure 59 ). the mouse pointer can be defined as any of the rom font characters. the 18x26 matrix is used to represent it. mouse pointer attributes the three 16-bit word attributes are located in os- dram: C mouse coding data C mouse pointer vertical position C mouse pointer horizontal position mouse pointer interrupt control the mouse pointer has a dedicated interrupt source which uses the same interrupt line as the osd. both interrupts (mouse pointer and osd) are simply ored at hardware level and forwarded to the cpu. the mouse pointer interrupt is generated as soon as the mouse matrix processing is completed. the mouse pointer interrupt generation is auto- matically enabled as soon as the mouse pointer is activated. to help identify the actual interrupt source, a flag (moit) is associated with the mouse pointer inter- rupt: this flag is activated when the mouse inter- rupt is generated and must be cleared by software. this bit is not the image of the interrupt transient condition but it keeps trace of the interrupt event until the software erases it. this bit must be reset by writing to the enable register. the mouse point- er interrupt is generated regardless of this flag val- ue.
138/268 - on screen display controller (osd) osd controller (contd) 8.5.7.1 mouse coding data address in segment 22h: 08h (bits 15:8), 09h (bits 7:0) bit 15 = mpfe mouse pointer fringe enable bit this bit is used to enable or disable the fringe on the mouse pointer. 0: no fringe. 1: the fringe is activated. bit 14 = mpre mouse pointer rounding enable bit this bit is used to enable or disable the rounding on the mouse pointer. 0: no rounding. 1: the rounding is activated. bit 13 = mfc4 mouse foreground palette this bit determines which palette is used for the mouse pointer color (independently of the setting of the pasw bit in the osddr register). 0: the basic foreground palette is used (address range in osdram: 10h - 2fh) 1: the extended foreground palette is used (ad- dress range in osdram: 50h - 6fh) bits 12:9 = mfc[3:0] mouse foreground color code these bits determine the foreground color of the mouse pointer. the mfc[3:0] value points to one of the 16 prede- fined entries of the foreground palette. for example, mfc[3:0] = 0 points to 10h & 11h if mfc4 = 0 (basic foreground palette), and points to 50h & 51h if mfc4 = 1 (extended foreground pal- ette). bit 8 = mpf8 mouse pointer character code extension this bit selects or deselects the character code ex- tension. 0: character code extension disabled. the ad- dressed character number range is 0 - 255. 1: character code extension enabled. the ad- dressed character number range is 256 - 383. bits 7:0 = mpf[7:0] mouse pointer character code this bit selects a character in the character font. the character is displayed in 18x26. if mpf8 = 0, the mfp[7:0] value range is 0 - 255. if mpf8 = 1, the mfp[7:0] value range is 0 - 127. 15 8 7 0 mpfe mpre mfc4 mfc3 mfc2 mfc1 mfc0 mpf8 mpf7 mpf6 mpf5 mpf4 mpf3 mpf2 mpf1 mpf0
139/268 - on screen display controller (osd) osd controller (contd) 8.5.7.2 mouse pointer vertical position address in segment 22h: 0ah (bits 15:8), 0bh (bits 7:0) bit 15 = mds mouse double size enable bit this bit enables or disables the double size display for the mouse pointer. 0: the mouse pointer is displayed in a 2y-2x size. 1: the mouse pointer is displayed in a 4y-4x size. bits 14:10 = free for the user bits 9:0 = mpy[9:0] mouse pointer vertical posi- tion these bits define the mouse pointer vertical start position expressed as a tv lines-per-field count (refer to figure 64 ). when the display controller works in non-interlaced mode, all mpy bits are used. when the display controller works in interlaced mode the mpy0 bit becomes meaningless the ac- tual mouse pointer starting position is given by mpy[9:1]. the minimum vertical shift is therefore a 2-pixel step, in interlaced mode, as incrementing the mouse pointer vertical position will act on both fields, producing a one line shift per field. in non- interlaced mode, the minimum vertical shift be- comes a 1-pixel step. warning: in interlaced mode the mpy0 bit must be forced by software to 0. 15 8 7 0 mds mpy9 mpy8 mpy7 mpy6 mpy5 mpy4 mpy4 mpy2 mpy1 mpy0
140/268 - on screen display controller (osd) osd controller (contd) 8.5.7.3 mouse pointer horizontal position bits 15:8: are at address 0ch in segment 22h. bits 7:0 are at address 0dh bits 15:11 = free for the user bits 10:0 = mpx[10:0] mouse pointer horizontal position these bits define the mouse pointer horizontal start position value expressed as a number of pixel clock periods. refer to figure 64 . figure 64. mouse pointer position 15 8 7 0 mpx10 mpx9 mpx8 mpx7 mpx6 mpx5 mpx4 mpx4 mpx2 mpx1 mpx0 mouse pointer character (18x26 matrix) vertical shift horizontal shift
141/268 - on screen display controller (osd) osd controller (contd) 8.5.8 programming the row buffers the 2 row buffers are based on the same structure ( figure 59 ): C next buffer start address C row mode C horizontal shift C row character count 8.5.8.1 next buffer start address and row mode address in segment 22h: 2p (bits 15:8), 2p + 1 (bits 7:0). see figure 59 . to display more than 1 character row on the screen, you must specify the start address of the next osdram row buffer (the row buffer contain- ing the next row to be displayed when the current row is completely processed). two bytes are re- served for this in the osdram. (see figure 59 ). as it is possible to display each row using different modes (serial, basic parallel, and extended paral- lel), the row mode has to be specified for the cur- rent row buffer. bits 15:14 = wm[2:1] serial/parallel row mode control these bits define the row mode for the buffer de- fined by the next buffer start address (nsa[8:0] bits). refer to table 25 for details. table 25. serial/parallel mode control bits 13:9 = free for the user bits 8:0 = nsa[8:0] next buffer start address these bits define the start address of the next row buffer. as row buffer start addresses are always even ad- dresses, the nsa0 is not implemented, and bit 0 is forced to 0 by hardware. 15 8 7 0 wm2 wm1 nsa8 nsa7 nsa6 nsa5 nsa4 nsa3 nsa2 nsa1 0 wm2 wm1 mode 1 1 (reserved) 1 0 extended parallel 0 1 basic parallel 0 0 serial
142/268 - on screen display controller (osd) osd controller (contd) 8.5.8.2 horizontal shift and row character count address in segment 22h: 2p + 2 (bits 15:8), 2p + 3 (bits 7:0). see figure 59 . for each row to be displayed, the number of char- acters in the row, and the horizontal position of the row on the screen need to be specified. lets assume that the start address of the current row buffer is 2p (even address). bits 15:10 = rcn[5:0] row character count these bits define the number of characters to dis- play in the current row. the display controller allows to display from 1 to 63 characters (in parallel mode) or 61 (in serial mode, as the first 2 bytes are taken as attributes).. for example, a 36 character row requires pro- gramming rcn[5:0] = 24h. bits 9:0 = hs[9:0] horizontal shift these bits define the horizontal shift value. they specify, in terms of number of pixel clock periods, the horizontal shift applied from the leading edge of the hsync pulse to the beginning of the first dis- played character (1 st character in parallel modes, 3 rd character in serial mode). refer to figure 65 . loading any value smaller than 01h is forbidden. the result is given by the formula: horizontal shift = [hs[9:0]+ 47] * (2*pixclk) (where pixclk is the clock issued from the skew corrector). refer to the timing and clock control chapter for programming information. figure 65. row position 15 8 7 0 rcn5 rcn4 rcn3 rcn2 rcn1 rcn0 hs9 hs8 hs7 hs6 hs5 hs4 hs3 hs2 hs1 hs0 st92x196 displayed row event line (vertical shift) horizontal shift
143/268 - on screen display controller (osd) osd controller (contd) 8.5.8.3 row attributes address in segment 22h: 2p + 4. see figure 59 . for each row to be displayed, specify the font ma- trix used (9x13 or 18x26), the size of the charac- ters, the rounding, the fringe and the flash mode. lets assume that the start address of the current row buffer is 2p (even address). bit 7 = fm font matrix this bit selects the 9x13 or the 18x26 font matrix for the current row. the fm bit is not an address extension bit but it af- fects how the font rom content is addressed. 0: the characters use a 9x13 font matrix. 1: the characters use an 18x26 font matrix bit 6 = uh upper half when 18x26 characters are displayed in double height (i.e. if the dbly parallel attribute is set), the uh bit defines if the current row displays the lower or upper half of the character. this bit has no effect when a 9x13 matrix is used or when the character has normal height (when dbly= 0). 0: the lower half of the double-height character is displayed. 1: the upper half of the double-height character is displayed. bit 5 = free for the user bit 4 = sy vertical size control bit this bit defines the character dot height refer to table 26 , table 27 , and table 28 for com- plete details. note : the dot height is also affected by dbly, de- fined in the parallel attribute section. bit 3 = sx horizontal size control bit this bit defines the character dot width refer to table 26 , table 27 , and table 28 for com- plete details. note : the dot width is also affected by dblx, de- fined in the parallel attribute section. table 26. 9x13 font matrix table 27. 18x26 font matrix (1) table 28. 18x26 font matrix (2) note : in 18x26 matrix mode, this mechanism pro- vides 7 different sizes which are: 1y-1x, 2y-2x, 4y-4x but also 2y-1x, 1y-2x, 4y-2x, 2y-4x. note : when the display controller works in basic parallel mode, the dblx and dbly bits are not ac- cessible, and are assumed to be always pro- grammed to 0. bit 2 = fon flash on control bit this bit is used to control the flashing period by software. it is only available in serial and extended parallel modes. this bit has no effect in basic par- allel mode. 0: the flashing mechanism is disabled for the whole row in all modes. 1: the flashing mechanism is enabled for the whole row. all characters described in the row with a serial or a parallel flash attribute are displayed as space with background color. underline also flashes. 70 fm uh sy sx fon rou fr sy sx dot height dot width matrix size 0 0 2 lines 2 pixels 1y-1x 0 1 2 lines 3 pixels 1y-1.5x 1 0 4 lines 3 pixels 2y-1.5x 1 1 4 lines 4 pixels 2y-2x sx character width dblx=0 dot width character width dblx=1 dot width 0 1x 1 pixel 2x 2 pixels 1 2x 2 pixels 4x 4 pixels sy vertical dot size dbly = 0 vertical dot size dbly = 1 0 1 line 2 lines 1 2 lines 4 lines
144/268 - on screen display controller (osd) osd controller (contd) bit 1 = rou rounding control bit this bit enables or disables the rounding for the whole row. 0: the rounding is disabled 1: the rounding is enabled note : for a 18x26 matrix size, there is no rounding when the character size is (1x,1y). for any other (x,y) size combinations, the rounding is possible for the 18x26 font matrix. bit 0 = fr fringe control bit this bit enables or disables the fringe for the whole row. the fringe mechanism can be activated for any size and matrix format. 0: the character fringe is disabled 1: the character fringe is enabled. note : in case of fringe usage in 1y vertical size and interlaced mode, a flicker may appear on screen as the fringe information is built on a field basis. 8.5.8.4 active range address in segment 22h: 2p + 5. see figure 59 . the active range feature is useful for software con- trolled smooth vertical scrolling (up or down). for each row to be displayed, the first line (rs) and the last line (re) to be displayed for the cur- rent row have to be specified. the two values (rs[3:0] and re[3:0]) are com- pared to the row line counter value. if the value of the counter is outside the active range (less than rs[3:0] or greater than or equal to re[3:0]), the border color is displayed as defined by its at- tributes. otherwise, if the counter value is inside the active range, the normal character pixel processing and display is done (see figure 66 ). lets assume that the start address of the current row buffer is 2p (even address). bits 7:4 = rs[3:0] active range start value the rs[3:0] value range is 0h-ch (0-12) in all cas- es (9x13 or 18x26 character matrix). bits 3:0 = re[3:0] active range end value the re[3:0] value range is 1h-dh (1-13) in all cas- es (9x13 or 18x26 character matrix). note : for 18x26 matrix characters, the active range is calculated by pair of tv lines, i.e. the ac- tive range always starts on the first field and finish- es on the second field (in interlaced mode). in case of non-interlaced display mode, the active range is calculated by pair of tv lines. figure 66. active range example 70 rs3 rs2 rs1 rs0 re3 re2 re1 re0 0 1 2 3 4 5 6 7 8 9 10 11 12 rs = 0 ; re = 13 rs = 4 ; re = 9 active range example pixel not displayed
145/268 - on screen display controller (osd) osd controller (contd) 8.5.8.5 serial mode in serial mode, only 1 byte is used to describe the character code or the attribute ( figure 59 ): C if the most significant bit (bit 7) of this byte is 0, the byte represents a character code. C if the most significant bit (bit 7) of this byte is 1, the byte represents a serial attribute. then the display controller uses bit 6 to determine wheth- er the attribute is a foreground serial attribute (bit 6 = 0) or a background serial attribute (bit 6 = 1). a consequence of this structure is that in serial mode, only the first 128 characters stored in the font rom can be accessed (the value of the 7 least significant bits of the character code = the character number in font rom). the first two bytes of the row buffer describing the row are displayed as border color. the first char- acter to be displayed in serial mode is in fact the 3 rd of the row buffer. all the attributes (background and foreground) are displayed as space with background color. lets assume that the start address of the current row buffer is 2p (even address). in this case the character codes and attributes are stored in the osdram at the address 2p+5+z, where z value is 1 to rcn (rcn is the row charac- ter count defined in section 8.5.8.2 ). character code in serial mode a ddress in segment 22h: 2p + 5 + z. see figure 59 . bits 6:0 = chc[6:0] character code in serial mode the chc[6:0] value points to one of the first 128 characters stored in the font rom. background serial attribute address in segment 22h: 2p + 5 + z. see figure 59 . bits 5:4 reserved bits 3:0 = bp[3:0] background palette pointer the bp[3:0] value points to one of the 16 prede- fined entries of the background palette for the background color and the translucency. for example, bp[3:0] = 0 points to the first back- ground palette entry, 30h & 31h if the palette swap bit pasw of the osddr register is reset (see reg- isters description for more details). note : the display of the background serial attribute is affected by the use of the italics (see the fore- ground serial attribute) and also by the m bit lo- cated in the background palette (see section 8.5.6.4 for further details). 70 0 chc6 chc5 chc4 chc3 chc2 chc1 chc0 70 1 1 x x bp3 bp2 bp1 bp0
146/268 - on screen display controller (osd) osd controller (contd) foreground serial attribute address in segment 22h: 2p + 5 + z. see figure 59 bit 5 = fla flash control bit this bit controls the flashing feature (see section 0.2.4.2). 0: all the following characters in the row are not af- fected by the flashing mechanism. 1: all the following characters in the row follow the flashing mechanism. note : flashing characters are alternatively dis- played as spaces and in normal mode (non-flash- ing), depending on the value of the fon bit in the row attribute byte (see section 8.5.8.3 ). the flash rate is controlled by software by toggling the "fon" bit. bit 4 = it italics control bit this bit enables the italic feature for the row. (see section 8.5.3.6 ) 0: italics are disabled. 1: all the following characters, until the end of the row, or the next foreground serial attribute are displayed in italics. note : italics mode is only available in serial mode. bits 3:0 = fp[3:0] foreground palette pointer the fp[3:0] value points to one of the 16 prede- fined entries of the foreground palette for fore- ground color, translucency and underline style of all the following characters (see section 8.5.6.3 ). for example, fp[3:0] = 0 points to the first fore- ground palette entry, 10h & 11h if the palette swap bit pasw of the osddr register is reset. 8.5.8.6 basic parallel mode in basic parallel mode, each character code (1 byte) is followed by a palette attribute (1 byte). see figure 59 . lets assume that the start address of the current row buffer is 2p (even address). in this case the character codes are stored in os- dram at the address 2p+4+2z, and the palette at- tributes are stored in the osdram at the address 2p+5+2z, where z ranges from 1 to rcn (rcn is the row character count defined in section 8.5.8.2 ). the character code structure allows pointing to the first 256 characters of the font rom (the character code value = the character number in font rom). character code in basic parallel mode address in segment 22h: 2p+4+2z. see figure 59 . bits 7:0 = chc[7:0] character code in basic par- allel mode the chc[7:0] value points to one of the first 256 characters stored in the font rom. palette attribute address in segment 22h: 2p+5+2z. see figure 59 . bits 7:4 = fp[3:0] foreground palette pointer the fp[3:0] value points to one of the 16 prede- fined entries of the foreground palette for the fore- ground color, the translucency and the underline style of all the following characters (see section 8.5.6.3 for further details). for example, fp[3:0] = 0 points to the first fore- ground palette entry, 10h & 11h if the palette swap bit pasw of the osddr register is reset (see reg- isters description for more details). bits 3:0 = bp[3:0] background palette pointer the bp[3:0] value points to one of the 16 prede- fined entries of the background palette for the background color and the translucency. for example, bp[3:0] = 0 points to the first back- ground palette entry, 30h & 31h if the palette swap bit pasw of the osddr register is reset (see reg- isters description for more details). note : the background color of the character is af- fected by the use of the m bit located in the back- ground palette (see section 8.5.6.4 ). 70 1 0 fla it fp3 fp2 fp1 fp0 70 chc7 chc6 chc5 chc4 chc3 chc2 chc1 chc0 70 fp3 fp2 fp1 fp0 bp3 bp2 bp1 bp0
147/268 - on screen display controller (osd) osd controller (contd) 8.5.8.7 extended parallel mode in extended parallel mode, each character code (1 byte) is followed by a palette attribute (1 byte) and a shape attribute (1 byte). refer to figure 59 . lets assume that the start address of the current row buffer is 2p (even address). the character codes are stored in the osdram at the address 2p+3+3z, the palette attributes are stored at the address 2p+4+3z, and the shape at- tributes are stored at the address 2p+5+3z, where z range value is 1 to rcn (rcn is the row charac- ter count defined in section 8.5.8.2 ). the character code structure, using the shape at- tribute, allows you to point to any of the font rom characters. the shape attribute definition depends on the font matrix used for the row (it depends on the fm bit, see section 8.5.8.3 ). character code in extended parallel mode address in segment 22h: 2p+3+3z. see figure 59 . bits 7:0 = chc[7:0] character code in extended parallel mode the chc[7:0] bits are used, combined with 3 or 1 bits of the shape attribute (for a 9x13 or 18x26 ma- trix), to point to any of the characters stored in the font rom (refer to the shape attribute description for more details). palette attribute address in segment 22h: 2p+4+3z. see figure 59 . refer to section 8.5.8.6 for the bit description. 70 chc7 chc6 chc5 chc4 chc3 chc2 chc1 chc0 70 fp3 fp2 fp1 fp0 bp3 bp2 bp1 bp0
148/268 - on screen display controller (osd) osd controller (contd) shape attribute - 9x13 matrix address in segment 22h: 2p+5+3z. see figure 59 . bit 7 = codx character code extension this bit is used with spl[1:0] as the character ad- dress extension. thus it is possible to address any of the 9x13 characters of the font rom. (see the spl[1:0] bit description for more details) bits 6:5 = spl[1:0] character split control bits these character split bits are used with the codx bit as the character address extension. it is then possible to address any of the 9x13 charac- ters of the font rom. if the character code is chc[7:0] (1 byte), then the character addressed with this structure is: codx.spl1.spl0.chc[7:0] bit 4 = fxp foreground extended palette ad- dressing bit this bit is combined with the pasw bit in the os- ddr register to give the msb bit of the foreground palette address. it allows the foreground palette, (basic or extended), to be selected on a per-char- acter basis. see table 29 for details. table 29. foreground palette selection bit 3 = bxp background extended palette ad- dressing bit this bit is combined with the pasw bit in the os- ddr register to give the msb bit of the back- ground palette address. it allows the background palette, (basic or extended), to be selected on a per-character basis. see table 30 for details. bit 2 = foc flash on character control bit this bit enables the flash mechanism for the cur- rent character. 0: the flash mechanism is disabled. the current character is displayed, whatever the flash row attribute value (fon) is (see section 8.5.8.3 ). 1: the flash mechanism is enabled. if the flash row attribute (fon) is on (see section 8.5.8.3 ), the character is displayed as space using the back- ground color. bit 1 = sha shadow mode control bit this bit enables or disables a black shadow shape on the right and bottom edges of the current char- acter foreground. 0: no shadow is added 1: a black shadow is added on the current charac- ter. note : this shadow shape follows the same algo- rithm as the fringe (see section 8.5.3.7 for further details). bit 0 = frc fringe on character control bit this bit enables or disables a fringe on the current character foreground. 0: no fringe is added. 1: a fringe is added on the current character if the fringe row attribute bit fr is set (see section 8.5.8.3 for more details). note : the fringe follows the algorithm described in section 8.5.3.7 . 70 codx spl1 spl0 fxp bxp foc sha frc pasw fxp foreground palette used 0 0 basic 0 1 extended 1 0 extended 1 1 basic pasw bxp background palette used 0 0 basic 0 1 extended 1 0 extended 1 1 basic
149/268 - on screen display controller (osd) osd controller (contd) shape attribute - 18x26 matrix address in segment 22h: 2p+5+3z. see figure 59 . bit 7 = codx character code extension this bit is used as the character address exten- sion. then it is possible to address any of the 18x26 characters of the font rom. lets assume that the character code is chc[7:0] (1 byte), then the character addressed with this structure is: codx.chc[7:0] bit 6 = dbly double height control bit this bit controls the double height feature applied on the current row height. 0: the character is displayed with the current row height, as defined by sy ( section 8.5.8.3 ). 1: the current character is displayed with a double height than defined by sy. the display of the lower or upper half of the character is controlled by the uh row attribute bit (refer to section 8.5.8.3 ). bit 5 = dblx double width control bit this bit controls the double width feature applied to the current row character width. 0: the character is displayed with the current width as defined by sx ( section 8.5.8.3 ). 1: the character is displayed in double width, ac- cording to the following rules: C it covers the next character location C the next character location is read and de- coded but not processed, C if the character is the last one in the row, it will be truncated to its left half. bits 4:0 = please refer to the bit descriptions in the 9x13 matrix shape attributes. 70 codx dbly dblx fxp bxp foc sha frc
150/268 - on screen display controller (osd) osd controller (contd) 8.5.8.8 row buffer management to start the display: 0. write the (dion, osde) bits to (1,0) to access the osdram with the cpu clock, 1. initialize the color palettes, 2. initialize the mouse pointer data (if needed), 3. initialize the first buffer start address with the address of the first byte of the above row buffer (address 0002h & 0003h of the segment 22h), 4. fill up one of the row buffers with the data to display the desired row (only in case the te bit in the osder register has been set), 5. initialize the event line value to the desired one (address 0000h & 0001h of the segment 22h), 6. set the mope bit (if needed), 7. start the display controller by programming the mode control bits (dion, osde) and the trans- fer enable bit (te) to the desired working mode. it is mandatory to start the display following the algorithm below: 1 unsigned char tmp; spp(osd_pg); /* select the osd register page */ osdfbr &= ~0x06; /* reset dint & moit bits */ 5 while (osdfbr & osdm_vsy); /* wait a low to high transition on vsync */ while (!(osdfbr & osdm_vsy)); tmp= osdmr; /* save lsm bits */ 10 osdmr &= ~0x07; /* reset the lsm bits so that the hsy bit will be an image of the hsync pulse */ osder = 0x40; /* osdram interface enabled with pixel clock */ di(); /* disable all interrupts */ 15 while (osdfbr & osdm_hsy); /* wait a hsync pulse : low -> high -> low transition */ while (!(osdfbr & osdm_hsy)); while (osdfbr & osdm_hsy); 20 osdmr = tmp; /* recover old lsm bit value */ spp(osd_pg); /* select the osd register page */ osder |= 0xe2; /* start the display by setting the appropriate bits, set at least osde, dion, and te bits. then set the other bits as required 25 for your application. here the mope (mouse pointer enable) bit is also set */ ei(); /* enable interrupts again*/
151/268 - on screen display controller (osd) osd controller (contd) the real time control provides: C a continuous search of matching values be- tween scan line and event line (this condition being evaluated at each tv line start). C a display interrupt generation when the match condition is detected. C in full osd mode, if the te bit in the osder register is set, the switch from one row buffer to the second row buffer when the match occurs. if the te bit in the osder register is reset, when a matching condition occurs, the previous row buff- er will be kept. 8.5.8.9 handling the row buffers in continuous mode: C when the line match condition is detected, an in- terrupt is sent to the cpu. let us then assume the te bit in the osder reg- ister is set. when the interrupt is executed: C the event line value must be programmed to the next desired value. C the next row buffer content must be filled up by the data of the next row to display. the next row buffer is easily identified using the bufl bit in the osdfbr register. let us then assume the te bit in the osder reg- ister is reset. when the interrupt is fetched: C the event line value must be programmed to the next desired value. C the next row buffer content might be filled up by the data of the next row to display, if desired. C the content of the current row buffer is not displayed but simply ignored as it should have al- ready been displayed in a previous cycle. note : in case the te bit in the osder register is kept reset, there is no need to manage the second row buffer as it will never be used.
152/268 - on screen display controller (osd) osd controller (contd) 8.5.9 register description to run the display controller properly, you need to program the 7 registers that configure the display border color register 2 (osdbcr2) r246 - read/write register page: 42 reset value: 0x00 0000 bit 7 = b2bc background to border color control bit . this bit allows to force the background color of all the characters to the border color. 0: all characters backgrounds are normally dis- played 1: all character backgrounds are forced to the cur- rent border color and translucency level. bit 6 = reserved bits 5:3 = bos[2:0] border color translucency these bits control the border color translucency. bos[2:0] = 7 means that the border color will be fully opaque (no video mixed in it on the display) bos[2:0] = 0 means that the border color will be fully transparent (the video is displayed instead of this color) bits 2:0 = bor[2:0] red border color these bits configure the red intensity for the bor- der color. bor[2:0] = 0 means that no red is used to define the border color. bor[2:0] = 7 means that the maximum red inten- sity is used in the border color. border color register 1 (osdbcr1) r247 - read/write register page: 42 reset value: 0x00 0000 bit 7 = difb digital fb control bit this bit selects the fast blanking (fb) output as analog or digital. 0: the fb dac works as an 8-level dac output from 0v up to 1v (with a 500ohms internal im- pedance to ground). 1: the fb dac works as a 2-level dac output, the high level providing an amplitude higher than 2.7 volts. all translucency control bits are man- aged as follows: - the code (0,0,0) generates a 0 output (0 volt), - all other codes generate a 1 output (>2.7 v). note : this applies to bt[2:0], ft[2:0], u2t[2:0], u2t[2:0] and bos[2:0] (refer to section 8.5.6.3 , section 8.5.6.4 and section 8.5.6.1 , and to the osdbcr2 register). bit 6 = reserved bits 5:3 = bog[2:0] green border color these bits configure the green intensity for the border color. bog[2:0] = 0 means that no green is used to de- fine the border color. bog[2:0] = 7 means that the maximum green in- tensity is used in the border color. bits 2:0 = bob[2:0] blue border color these bits configure the blue intensity for the bor- der color. bob[2:0] = 0 means that no blue is used to define the border color. bob[2:0] = 7 means that the maximum blue inten- sity is used in the border color. 70 b2bc bos2 bos1 bos0 bor2 bor1 bor0 70 difb - bog2 bog1 bog0 bob2 bob1 bob0
153/268 - on screen display controller (osd) osd controller (contd) enable register (osder) r248 - read/write register page: 42 reset value: 0000 0000 (00h) bit 7 = dion display on this bit is used in combination with the osde bit to control the display working mode. see table 31 . warning : after a reset, a valid hsync signal is re- quired to write to the osdram, whatever the clock rate (cpu or pixel clock rate). bit 6 = osde osd enable this bit is used in combination with the dion bit to control the display working mode. see table 24 . note 1 : when the (dion,osde) bits switch from any other value to (1,1), i.e. when the controller is switched to a full osd function, the first buffer start address content is used to locate the first row buffer to process. while the full display function is running, the dion & osde bits remain set and the first buffer start address is not used again, even if both bits are re- written to 1. note 2 : it is strongly recommended to use state 3 only if the osdram has been initialized using state 2. warning 1: states 3 and 4 (refer to table 31 ) can only be used if hsync and vsync are applied on the external pins. warning 2 : after a reset, a valid hsync signal is required to write to the osdram, regardless of the clock rate (cpu or pixel clock rate). warning 3 : when the osd is displayed, it is ad- vised not to write to the osdram when a vsync pulse occurs. in normal operating mode, this con- figration will never happen. bit 5 = te transfer enable bit this bit controls the swap to next row buffer func- tion whenever the scan line counter content matches the event line parameter value. an interrupt request pulse is generated and for- warded to the core each time the match occurs re- gardless of the value of te. 0: row buffer swap disabled. the current row buff- er content is simply ignored and the screen will display the border color, as if the current buffer content was already processed. 1: a row buffer swap enabled note : refer to section 8.5.8.8 for more details about using the te bit. bit 4 = dbls double scan bit this bit defines if the display works in 1h or 2h mode. 0: the display works in single scan or 1h mode. 1: the display works in double scan or 2h mode. the 2h mode is used in progressive scan display (60hz field, 525 lines). note : the dbls bit acts on the display vertical de- lay for field determination (refer to the vd[3:0] bits of the delay register osddr). the dbls bit also acts on the line start mute (re- fer to the lsm[2:0] bits of the mute register osd- mr) and the hsy flag bit. table 31. osdram interface configuration 70 dion osde te dbls nids tsle mope fpixc dion osde osdram interface clock osd function detailed configuration state 0 0 off, no ram access off the osdram controller and the display are both disa- bled. the cpu has no access to the osdram. 1 1 0 on, cpu clock off the display is disabled. the osdram controller is run- ning using the cpu clock, allowing for cpu accesses. 2
154/268 - on screen display controller (osd) 0 1 on, pixel clock no osd, time control on the display is partially enabled. the osdram control- ler is running with the pixel clock, allowing cpu access- es. the osd pixel processing is disabled (rgb & fb outputs are turned off), the tv oriented time control is still running, such as event line control, interrupt genera- tion, flag bits and field calculation. the border control is inactive. 3 1 1 on, pixel clock fully on the osdram controller and the display are both ena- bled. the osdram controller is running with the pixel clock, allowing cpu accesses. the rgb & fb outputs are turned on. the border control is activated. 4
155/268 - on screen display controller (osd) osd controller (contd) bit 3 = nids non interlaced display control bit this bit selects the interlaced or non-interlaced mode. 0: the display works in interlaced mode (line counting, fringe and rounding algorithms are 2- field based) 1: the display works in non-interlaced mode (line counting, fringe and rounding algorithms are 1- field based). bit 2 = tsle translucency enable bit this bit enables or disables the digital translucen- cy signal (tslu) generation. (refer to the section 8.5.3.11 ). 0: the tslu signal built by the display controller remains continuously idle regardless of the osd activity. 1: the tslu signal carries the real time back- ground information and can be output through the i/o pin alternate function. bit 1 = mope mouse pointer enable . this bit enables or disables the mouse pointer. 0: the mouse pointer is disabled 1: the mouse pointer is enabled. note : when the mouse pointer feature is not im- plemented, this bit becomes "reserved". the mope bit also acts as a mouse pointer inter- rupt enable: enabling the mouse pointer allows automatically enables the mouse pointer interrupt generation. bit 0 = fpixc fast pixel clock control bit this bit handles the divide-by-2 prescaler inserted between the skew corrector output and the dis- play pixel clock input. 0: the skew corrector clock output is divided by 2 to provide the pixel clock. 1: the skew corrector clock output is directly tak- en as the pixel clock. note : for further information, refer to the timing and clock control chapter.
156/268 - on screen display controller (osd) osd controller (contd) delay register (osddr) r249 - read/write register page: 42 reset value: 0xxx xxxx note : the display may flicker if you write to the delay register while osd is fully on. bit 7 = pasw palette swap bit the pasw bit is used in serial or basic parallel modes to provide access to the extended palettes. it is still active when you work in extended parallel mode, however it not needed as the fxp and bxp bits are available (refer to section 8.5.8.7 ). 0: the basic palette sets are used. 1: the extended palette sets are used. bit 6 = hpol hsync signal polarity selection bit this bit has to be configured according to the po- larity of the hsync input signal. 0: hsync input pulses are of positive polarity 1: hsync input pulses are of negative polarity bit 5 = vpol vsync signal polarity selection bit this bit has to be configured according to the po- larity of the vsync input signal. 0: vsync input pulses are of positive polarity 1: vsync input pulses are of negative polarity bit 4 = fbpol fast blanking signal polarity selec- tion bit this bit selects the polarity of the fast blanking (fb) output signal. 0: fb output pulses are of positive polarity (fb ac- tive high) 1: fb output pulses are of negative polarity (fb ac- tive low) note : the fb signal is kept active during the vsync vertical retrace. bits 3:0 = vd[3:0] vertical delay control bits this 4-bit value is used to program an internal de- lay on vertical sync pulses applied to vsync input pin. the purpose of the programmable delay is to pre- vent vertical osd jitter in case the rising edge of external vertical sync pulse coincides with thatofan external horizontal sync pulse. the delay applied is expressed by the following equations (4 mhz is the frequency issued directly from the crystal oscillator): for 2h display mode: [vd[3:0]+1] * 8*(1/4mhz) =< d =< [vd[3:0]+2] * 8*(1/4mhz) for 1h display mode: [vd[3:0]+1] *16*(1/4mhz) =< d =< [vd[3:0]+2] *16*(1/4mhz) note : programming the vertical delay to fh will freeze the scan line counter disabling any further rgb output. note : it is mandatory for the cpu to initialize the vertical delay register to avoid any problems. 70 pasw hpol vpol fbpol vd3 vd2 vd1 vd0
157/268 - on screen display controller (osd) osd controller (contd) flag bit register (osdfbr) r250 - read/write register page: 42 reset value: xxxx xxxx (xxh) bit 7 = bufl buffer flag bit this bit indicates which row buffer of the osd ram is being used by the display. the bufl flag is automatically re-evaluated each time the scan & event line matching condition is fulfilled. in case the te bit is reset (see the os- der register), the bufl flag remains un- changed as no row buffer change occurs. 0: the osd displays the content of the second row buffer (the one not pointed by the first buffer start address value). 1: the osd displays the content of the row buffer location pointed by the first buffer start address value. note : the bufl flag is automatically reset when the (dion,osde) bits are switching from any oth- er value to (1,1); it will be set at the first buffer transfer (scan & event match and te=1). bit 6 = vsy vsync status bit this bit gives the status of the vsync input signal. 0: the vsync input signal is inactive. 1: the vsync input signal is active. note : the vsync signal polarity is compensated to always provide vsy=1 during the vertical pulse. bit 5 = hsy hsync status bit this bit gives the status of the internal hs signal generated by the skew corrector and locked to the external hsync signal. 0: the hs signal is inactive. 1: the hs signal is active. note : the hsync signal polarity is compensated to provide hsy=1 during the horizontal pulse. note : hsy remains active during the whole line start mute timing which is software controlled through both the dbls bit and the lsm[2:0] value (see osder and osdmr registers). bit 4 = vsdl delayed vertical pulse status bit this bit indicates the status of the vdpls internal signal (it is the delayed vertical pulse issued from the programmable vertical delay unit as described by the osddr register bits vd[3:0]) 0: the vdpls internal signal is inactive 1: the vdpls internal signal is active note : the vdpls signal polarity is compensated to provide vsdl =1 during the vertical pulse. bit 3 = field field status bit this bit indicates the current tv field. 0: tv beam is in field 2 (even field) 1: tv beam is in field 1 (odd field) bit 2 = dint display interrupt flag bit this bit is set by hardware when an osd interrupt occurs. this bit must be reset by software. refer to table 32 . table 32. display and mouse interrupt flags note : to handle osd interrupts, it is recommend- ed to clear the pending bit associated with the ex- ternal interrupt channel used for the osd (see the chapter on interrupts) and then poll the two flag bits (dint & moit) in series within the display in- terrupt routine. bit 1 = moit mouse pointer interrupt flag . this bit indicates which is the source of the osd interrupt (see table 32 ). this bit must be reset by software. bit 0 = sl8 most significant bit of the scan line counter refer to the description of the osdslr register. 70 bufl vsy hsy vsdl field dint moit sl8 dint moit meaning 0 0 no interrupt 0 1 mouse interrupt 1 0 display interrupt 11 mouse and dis- play interrupts
158/268 - on screen display controller (osd) osd controller (contd) scan line register (osdslr) r251 - read only register page: 42 reset value: xxxx xxxx (xxh) bits 7:0 = sl[7:0] scan line counter value these bits indicate the current vertical position of the tv beam. the most significant bit sl8 of this counter is locat- ed in the flag bit register osdfbr (see below). this counter starts from 0 at the top of the screen (i.e. after the vsync pulse) and is incremented by hsync. mute register (osdmr) r252 - read/write register page: 42 reset value: 00xx x000 bit 7 = admult address multiply control bit this bit, together with the odevn bit, controls the, osdram address generation. (refer to the note below for more details) 0: the cpu address is used to address the os- dram, i.e. the cpu address lsb bit is used as osdram address lsb. 1: the cpu address is multiplied by 2 and the odevn control bit is used as the osdram lsb address bit. note : this mechanism is intended for improved software compatibility with the st9296 when the display works in basic parallel mode; it allows to do a buffer transfer to the osdram using a basic "ld memory-to-memory with post-increment" in- struction; i.e.: ld(..)+, ('')+ to fill up the row buffer, making an automatic reservation for the attribute byte associated with the character. bit 6 = odevn odd/even address control bit this bit controls the osdram address lsb bit when the admult bit is high. refer to the admult bit description for further de- tails. bits 5:3 are reserved bits 2:0 = lsm[2:0] line start mute value these bits are used to program the mute duration after the beginning of each tv line. when the display works in 1h mode the mute du- ration can be adjusted in 2s steps from 2 to 14 s. when the display works in 2h mode the mute du- ration can be adjusted in 1s steps from 1 to 7 s. the lsm bits also define the hsy flag duration. the mute duration is expressed by the following equation (the 1s is a frequency issued from the crystal oscillator): for 2h display mode: t mute = lsm[2:0] * (1 s) for 1h display mode: t mute = lsm[2:0] * 2*(1 s) in both 1h/2h modes, if lsm[2:0] = 0 then t mute = hsync width. 70 sl7 sl6 sl5 sl4 sl3 sl2 sl1 sl0 70 admult odevn - - - lsm2 lsm1 lsm0
159/268 - on screen display controller (osd) osd controller (contd) table 33. osd register map register number page 42 register name 765 4 3210 246 osdbcr2 b2bc - bos2 bos1 bos0 bor2 bor1 bor0 247 osdbcr1 difb - bog2 bog1 bog0 bob2 bob1 bob0 248 osder dion osde te dbls nids tsle mope fpixc 249 osddr pasw hpol vpol fbpol vd3 vd2 vd1 vd0 250 osdfbr bufl vsy hsy vsdl field dint moit sl8 251 osdslr sl7 sl6 sl5 sl4 sl3 sl2 sl1 sl0 252 osdmr admult odevn - - - lsm2 lsm1 lsm0
160/268 - closed caption data slicer (ds) 8.6 closed caption data slicer (ds) 8.6.1 introduction depending on the st9 device, one or two data slicers may be available in the mcu (refer the de- vice feature list and register map). each data slicer can extract either n closed caption data from a composite video signal broadcast in the eia-608 format. used in conjunction with the osd, it allows closed caption information to be displayed on a tv screen. n gemstar format data transmitted on one or more horizontal lines in the vertical blanking interval. in this format, one line contains 4 bytes of data. the data slicer automatically determines the data format in the specified line and sets the appropri- ate flag. 8.6.2 functional description inputs ccvideo: composite video signal ac coupled through a 1f capacitor. hsync: horizontal deflection pulse. vsync: vertical deflection pulse. f_4mhz: 4 mhz clock from frequency multiplier. outputs irq: conditional negative edge interrupt request, connected to a cpu interrupt channel (see interrupts chapter). as shown in figure 67 , the data slicer accepts the incoming composite video as an ac coupled sig- nal through a 1f capacitor to the ccvideo pin. the osd synchronization signals and a 4 mhz crystal derived clock are used in the data slicer signal extraction logic. data extraction can be programmed for a selecta- ble line in either field for a video signal of ampli- tude of 2v +/-3db. the slicing level for data is con- trolled automatically by hardware. the output signal dsout is high when the input signal exceeds the level of the reference voltage vslice, and low when it is less than vslice. the clamp is disabled from the time of detection of vertical sync in ccvideo (a sync pulse wider than 12s) up to line 28. note: for good slicing results, it is advised to set vdda >= 5.3v. remember also that vdda < vdd + 0.3v. figure 67. block diagram - + - + - + data processor up/down counter data registers status register clock generator clamp interrupt 4 mhz (from frequency multiplier) csync vref (black) vref (sync) ccvideo 1f vslice vref
161/268 - closed caption data slicer (ds) data slicer (contd) 8.6.3 data slicer operation the data slicer is enabled or disabled using the eds bit in the dr1 register. the data slicer clock frequencies are generated by the clock generator starting from a basic 4 mhz clock. the decoder is activated when the output of a half- line counter matches the value written by the user in the cr1 register and a horizontal sync pulse is detected while the match is valid. odd values of half-line counts in register cr1 are used to decode lines in field#1, even values to decode lines in field#2. the cc decoder includes logic for recog- nizing the current field and generates a corre- sponding field1 signal. the slicing level is automatically adjusted during the clock run-in window to obtain approximately a 50% duty cycle waveform corresponding to the clock run-in signal at the data slicer output. refer to figure 68 . dsout is fed into the data processor where it is processed for the selected line. the waveforms of dsout at the output of the comparator for signals received in either closed caption or gemstar for- mat are shown in figure 68 . the closed caption signal starts with 7 cycles of clock run-in signal with a frequency of about 500khz, and ends with 16 bits (2 bytes) of data where each bit has a peri- od of approximately 2s. the gemstar signal has only 5 cycles of the 500khz clock run-in signal and transmits 32 bits (4 bytes) of data with the period of each bit reduced to about 1s. closed caption and gemstar signals are detected by looking for their distinctive frame codes. frame code refers to the characteristic of the signal waveform in a time interval between the clock run- in and data sections of the signal as shown in fig- ure 68 . the frame code detector examines during a 5s window selected outputs of a 32-stage shift register which holds consecutive samples of dsout obtained with a 4mhz clock at.25s inter- vals. in normal operation the frame code detector requires the 5 bits marked with an upward pointing arrow (^) to be correct, but in a search mode cov- ering all lines in the vertical blanking interval all 8 bits of the frame code are examined by when the search control bit in the cr2 register is set. identification of the frame code results in setting either the ccmode or gsmode bit in the mr register. then the clock for recovering the follow- ing 2 or 4 data bytes is activated in correct phase relative to the data signal. parity of all data bytes is checked and appropriate flags evnp[4:1] are set correspondingly in the mr register. an interrupt is always generated at the end of the specified line and on the corresponding line of the opposite field, even if no data has been recovered. the data slicer is able to recover data from 2 or more adjacent lines. however, except for the last line to be decoded in the current field, in such a sit- uation recovered data bytes must be read out with- in a time period of 18s after an interrupt has oc- curred. during normal operation, the interrupt should oc- cur at the end of the selected line. however, if data must be recovered from adjacent lines in the same field, then it becomes necessary for some of the lines to generate an interrupt at the leading edge of interrupt signal, and thereafter for the same line at the trailing edge of the interrupt signal. the irq_inv bit in the cr1 register controls the po- larity of the interrupt signal. the ted0 bit in the eitr register should be set to 1 and inv_irq should be used to control the data slicer interrupt polarity.
162/268 - closed caption data slicer (ds) data slicer (contd) figure 68. data slicer waveforms 32 data bits @ 993ns 16 data bits @ 2us clock run-in clock run-in frame code frame code 1 1 0 0 0 0 01 00 111 11 1 ^ ^ ^ ^ ^^ ^ ^ ^ ^ closed caption signal (dsout) gemstar signal (dsout) 8s 5s clock run-in window frame code window horizontal sync (csync) interrupt irq interrupt w/ irq_inv=1 interrupt w/ irq_inv=0 ccirq for irq_inv=1 ccirq for irq_inv=0
163/268 - closed caption data slicer (ds) data slicer (contd) 8.6.4 interrupt handling if the device has two data slicers, both use the same interrupt channel. so some additional soft- ware is needed, when using both slicers at the same time. using only one of them (i.e. ds0) al- lows for software compatibility with the st9296. the interrupt requests, issued by the two slicers are ored in order to generate an interrupt signal on the same st9 interrupt channel. the internal signals irq1 for ds0 / irq2 for ds1 (see figure 68 ) are activated when the line number matches the value set by the user in the first control register and this signal is reset at the end of the line: the irq_inv bit in the cr1 register allows to select whether the rising edge or the fall- ing edge of this signal will cause a positive pulse on ccirq1 or ccirq2. as the ccirq pulses are very short, the ted0 control bit in the eitr regis- ter is of very limited use. it is recommended to keep this bit always at 1 (interrupt on rising edge). in order to find out the source of an interrupt re- quest, each of the two slicers sets the irfl bit in the cr2 register when an interrupt request is is- sued. both of these flags (irfl for ds0 and ds1) must be scanned and then cleared by the software during every interrupt service routine. note: there are situations where data has to be recovered from one or more lines in only one field, i.e. either field#1 or field#2. in such cases an un- necessary interrupt is generated in the field that does not contain any lines with data that is of inter- est. for example, to recover closed caption data on line#21 in field#1, the half line count ln[5:0] in the cr1 regsiter can be permanently set to 33. this value of ln[5:0] will also cause an interrupt to be generated in the middle of line#21 in field#2. the interrupt routine must therefore determine the status of the field1 bit in the mr register and im- mediately return to the main program if this bit is low. note: an interrupt is always generated at the end of the specified line (and on the corresponding line of the opposite field).
164/268 - closed caption data slicer (ds) data slicer (contd) 8.6.5 register description the register description lists the register page for data slicer 0 (ds0) if a second data slicer is avail- able (ds1), it is mapped in page 46. data register 1 (dr1) r240 - read only register page: 45 reset value: 0000 0000 (00h) bit 7:0 = d1[7:0]: first data byte for gemstar data register 2 (dr2) r241 - read only register page: 45 reset value: 0000 0000 (00h) bit 7:0 = d2[7:0]: second data byte for gemstar data register 3 (dr3) r242 - read only register page: 45 reset value: 0000 0000 (00h) bit 7:0 = d3[7:0]: third data byte for gemstar, first data byte for closed caption 70 d1.7 d1.6 d1.5 d1.4 d1.3 d1.2 d1.1 d1.0 70 d2.7 d2.6 d2.5 d2.4 d2.3 d2.2 d2.1 d2.0 70 d3.7 d3.6 d3.5 d3.4 d3.3 d3.2 d3.1 d3.0
165/268 - closed caption data slicer (ds) data slicer (contd) data register 4 (dr4) r243 - read only register page: 45 reset value: 0000 0000 (00h) bit 7:0 = d4[7:0]: fourth data byte for gemstar, second data byte for closed caption control register 1 (cr1) r244 - read/write register page: 45 reset value: 0000 0000 (00h) bit 7 = stndby : standby mode this bit selects the standby mode (operation when main power supplies have been turned off). 0: the horizontal deflection pulses (hpls) are used for synchronization 1: horizontal synchronization pulses are internally generated from the incoming video signal (verti- cal synchronization signal for the data slicer is always derived from incoming video). bit 6 = irq_inv: interrupt signal polarity. this bit is set and cleared by software. it controls the position of the data slicers interrupt signal to the p (ccirq) to be on the rising or falling edge of the slicers interrupt signal (irq). refer to figure 68 . it is used to setup the interrupt to occur at the beginning of the specified line or at the end of the line. 0: the interrupt request occurs at the end of the specified line 1: the interrupt request occurs at the beginning of the specified line. note: data recovery from adjacent lines: in situations where closed caption or gemstar data has to be recovered from adjacent lines, e.g. from line#20 and line#21 in field#1, it becomes necessary to generate an interrupt both at the ris- ing edge as well as at the falling edge of the irq signal shown in figure 68 . the interrupt at the ris- ing edge of irq for line#20 is obtained by setting the irq_inv bit and writing the ln[5:0] value for line#21 in the cr1 register. usually it will be too late to write this value at the end of line#20. after the ln[5:0] value for line#21 has been written, the software must also clear the irq_inv bit before exiting the interrupt routine. this will cause the next interrupt to be generated at the falling edge of irq which occurs at the end of line#20. at this time the character codes transmitted in line#20 are available for reading. bit 5:0 = ln[5:0]: closed caption line selector. the data slicer current half-line count is compared with the ln[5:0] value; the half-line counter is re- leased from the reset state when the first vertical sync pulse is detected. with the ntsc standard, to select line n the ln[5:0] value must be set to ln[5:0] = [(2*n)-9] for field#1, and [(2*n)-8] for field#2. examples: ln[5:0] = 33 (21hex) for line#21 in field 1, ln[5:0] = 34 (22hex) for line#21 in field 2. control register 2 (cr2) r245 - read/write register page: 45 reset value: 0000 0000 (00h) bit 7 = eds: enable data slicer. this bit is set and cleared by software. 0: disable data slicer (analog part) 1: enable data slicer bit 6 = irfl: interrupt flag . this bit is set by hardware, when an interrupt re- quest is issued. it must be cleared by software when the corresponding interrupt service routine has been finished. a clear can be performed by any write operation to this register. 0: no data slicer interrupt pending 1: data slicer interrupt pending bit 5 = ccid: external interrupt source selection. this bit is set and cleared by software. 0: the interrupt request from the data slicer is for- warded to the cpu 1: the interrupt from the external interrupt pin is forwarded to the cpu. 70 d4.7 d4.6 d4.5 d4.4 d4.3 d4.2 d4.1 d4.0 70 stnd by irq_ inv ln5 ln4 ln3 ln2 ln1 ln0 70 eds irfl ccid sea rch scg _en phd 2 phd 1 phd 0
166/268 - closed caption data slicer (ds) data slicer (contd) bit 4 = search: enhanced signal search. this bit is set and cleared by software. this bit should be set to improve the reliability of properly identifying signals in closed caption and gemstar format when doing a search encompassing all hor- izontal lines in the vertical blanking interval. 0: check 5 bits in the frame code 1: check 8 bits in the frame code bit 3 = scg_en: block copy-guard signals. in video signals with copy-guard protection puls- es similar to horizontal sync pulses may have been inserted into certain lines in the vertical blanking interval. 0: no blocking 1: copy-guard pulse occurring 8 s before the an- ticipated occurrence of normal horizontal sync pulses are blocked from reaching the line detec- tion logic bit 2 = phd[2:0]: horizontal phase compensation. these bits specify the delay added in 4s incre- ments to the clock for the half-line counter in logic that identifies the specified line. this feature is used in 2h mode of operation to compensate for a large phase difference which may exist between 2h deflection pulses and horizontal sync pulses extracted from video. monitor register (mr) r246 - read/write register page: 45 reset value: 0000 0000 (00h) bit 7 = ccmode: closed caption mode. this bit is set by hardware and cleared by soft- ware. 0: no closed caption format detected 1: closed caption format detected bit 6 = gsmode: gemstar mode. this bit is set by hardware and cleared by soft- ware. 0: no gemstar format detected 1: gemstar format detected bit 5= field1: field 1 flag. this bit is set and cleared by hardware. 0: field 2 detected 1: field 1 detected warning: the bit value is not valid after tuning of a new channel or in case of a momentary drop-out of the tuned signal. in this case, the use of the in_sync bit is required. bit 4= in_sync: phase of line monitoring relative to video field. this bit is set and cleared by hardware. software should read this bit periodically in case data in closed caption and/or gemstar format must be re- covered from lines in both fields (e.g. closed cap- tions from line#21 of field1 and extended data service information from line#21 of field2). 0: periodic writing of the appropriate line codes into register cr1 is out of phase with the field sequence of the video input signal. in this case the phasing can be corrected by skipping just once the change of the line code stored in the cr1 register and writing the immediately follow- ing field. 1: the start of a specified line has been detected in one or both of the last 2 fields. note: in situations where the closed caption or gemstar data is on lines which are all in the same field, e.g. field#1, the hardware in the data slicer cell will automatically correct an out-of-phase situ- ation. such a situation will be corrected within the period of one frame of video. in a more general situation, data must be recov- ered from lines in both fields, and then the hard- ware cannot on its own correct the polarity of an out-of-phase field#1 signal. the correction must therefore be done by software on basis of informa- tion provided by the in_sync status bit. bit 3:0= evnp[4:1] : parity event bits these bits are set and cleared by hardware. they indicate the detected parity of data bytes 1 through 4 (only 3 and 4 for closed caption format). these bits should normally be low. 0: odd parity detected 1: even parity detected 70 cc mode gs mode field 1 in_sy nc evnp 4 evnp 3 evnp 2 evnp 1
167/268 - closed caption data slicer (ds) table 34. ds register map register number page 45 register name 765 4 3210 240 dr1 d1.7 d1.6 d1.5 d1.4 d1.3 d1.2 d1.1 d1.0 241 dr2 d2.7 d2.6 d2.5 d2.4 d2.3 d2.2 d2.1 d2.0 242 dr3 d3.7 d3.6 d3.5 d3.4 d3.3 d3.2 d3.1 d3.0 243 dr4 d4.7 d4.6 d4.5 d4.4 d4.3 d4.2 d4.1 d4.0 244 cr1 stndby irq_inv ln5 ln4 ln3 ln2 ln1 ln0 245 cr2 eds irfl ccid search scg_en phd2 phd1 phd0 246 mr ccmode gsmode field1 in_sync evnp4 evnp3 evnp2 evnp1
168/268 - video sync error detector (syncerr) 8.7 video sync error detector (syncerr) 8.7.1 functional description the sync error detector provides information to the tuning system whether an if signal is a picture carrier or not. the csync source for the detector is selected using the sysel[1:0] bits in the irscr register: it is internally extracted fro ccvideo1 and 2 or directly taken from the syndet1 or syndet0 pins. the number of positive transitions of csync in a 78sec window is checked. one or two transitions should occur in every window (horizontal sync pulses occur at intervals of 63.5s). an error coun- ter is incremented at end of a window in case of one or more of the following situations : 1.no low to high transitions of the signal were de- tected within the 78s wide window. 2.more than 2 low-to-high transitions were detect- ed within the window. 3.more than 2 consecutive samples of csync taken at 8s intervals within the window were high. the errors are accumulated for a period of one field as defined by two adjacent vertical deflection pulses. then the error count for the field is latched into the syncer register and the valid flag is set. the frequency of pulses applied to syndet0 or syndet1 input not producing any errors is in the range of 13khz to 25khz. the width of the pulses applied to these inputs and not producing any er- rors is less than 16us. inevitably, error counts are generated in the verti- cal sync interval in presence of double frequency equalization and wide sync pulses. with a stand- ard video signal the typical error count is 5. the er- ror count threshold for an acceptable video signal can be set on basis of experimental results with a typical value of about 30. 8.7.2 register description sync error register (syncer) r249 - read only, except bit 7 register page: 43 reset value: 0000 0000 (00h) bit 7 = valid: data valid bit this bit is set by hardware on the leading edge of a vertical deflection pulse. it is cleared by software bit 6:0 = sd[6:0] : sync error count these bits are updated by hardware on the lead- ing edge of a vertical deflection pulse. ir/sync control register (irscr) r250 - read/write register page: 43 reset value: 0000 0000 (00h) bit 7:6 = reserved. forced by hardware to 0. bit 5, 0 = sysel[1:0] : sync error detector input selection bit 4:1 = reserved (used for ir preprocessor). re- fer to the ir preprocessor chapter. 70 valid sd6 sd5 sd4 sd3 sd2 sd1 sd 0 70 0 0 sysel1 - - - - sysel0 sysel1 sysel0 00 csync signal on syndet0 input 01 csync signal on syndet1 input 10 csync extracted from ccvideo1 11 csync extracted from ccvideo2
169/268 - ir preprocessor (ir) 8.8 ir preprocessor (ir) 8.8.1 functional description the ir preprocessor measures the interval be- tween adjacent edges of the demodulated output signal from the ir amplifier/detector. you can specify the polarity using the posed and neged bit in the irscr register the measurement is rep- resented in terms of a count obtained with a 12.5khz clock and stored in the irpr register. whenever an edge of specified polarity is detect- ed, the count accumulated since the previously detected edge is latched into an 8-bit register and an interrupt request irq is generated if the ir- wdis bit is reset in the irscr register. note: any count less than 255 stored in the latch register is over-written in case the p fails to exe- cute the read before the next edge occurs. in case an edge is not detected in about 20ms (the count reaches its maximum value of 255) the count is latched immediately and the irq flag is set. an overflow flag (not accessable) is also set internally. each time an interrupt is received, it must be ac- knowleged by writing any value in the irpr regis- ter. otherwise no further interrupts will be generat- ed. warning: the content of the latch cannot be changed as long as the overflow flag remains set. to clear the irq and internal overflow flags, just write any value in the irpr register. as long as the internal overflow flag is set, no interrupt is generat- ed. the ir input signal is preprocessed by a spike fil- ter. the flsel bit of the irscr register deter- mines the width of filtered pulse. 8.8.2 register description ir pulse register (irpr) r248 - read only register page: 43 reset value: 0000 0000 (00h) bits 7:0 = ir[7:0] : ir pulse width in terms of number of 12.5khz clock cycles. ir/sync control register (irscr) r250 - read/write register page: 43 reset value: 0000 0000 (00h) bit 7:6 = reserved. forced by hardware to 0. bit 5 = reserved (used for sync error detector). refer to the sync error detector chapter. bit 4 = irwdis : external interrupt source. this bit is set and cleared by software. it selects the source of the interrupt assigned to the external interrupt channel. refer to the interrupt chapter. 0: the interrupt request from the ir preprocessor is forwarded to the cpu 1: the interrupt from the external interrupt pin is forwarded to the cpu bit 3 = flsel : spike filter pulse width selection this bit is set and cleared by software. it selects the spike filter width. 0: filter pulses narrower than 2s 1: filter pulses narrower than 160s bit 2:1 = posed , neged edge selection for the duration measurement bit 0 = reserved (used for sync error detector). 70 ir7 ir6 ir5 ir4 ir3 ir2 ir1 ir 0 70 0 0 - irwdis flsel posed neged - neged posed count latch at ... 11 positive or negative transition of ir or when count reaches 255 10 negative transition of ir or when count reaches 255 01 positive transition of ir or when count reaches 255 0 0 only when count reaches 255
170/268 - four-channel i 2 c bus interface (i2c) 8.9 four-channel i 2 c bus interface (i2c) 8.9.1 introduction the i 2 c bus master/slave interface supports up to 4 serial i 2 c buses used for communication with various external devices. it meets all of the re- quirements of the i 2 c bus specification (except ex- tended 10-bit addressing compatibility for slave operation and cbus compatibility). 8.9.1.1 general features C conversion of internal 8-bit parallel data to/from external i 2 c bus serial data C realtime interrupt generation and handling C software selectable operation one of four i 2 c buses C software selectable acknowledge bit generation C internal general reset C 8-bit data read/write register C 8-bit control register, C 8-bit status register, C operates by default in slave mode and is auto- matically switched to master mode by loading the data write register when the bus is idle. 8.9.1.2 master operation C 4-bit frequency control register to select 1 of 16 clock frequencies for the scl line ranging from 20 khz to 800 khz derived from a 4mhz crystal clock C compatible with standard 7 or extended 10-bit address protocol C handles stretching of scl bus clock pulses by slaves without restrictions C bus arbitration with arbitration loss detection in multimaster environment C bus error detection C optional push-pull bus drive capability for faster communication 8.9.1.3 slave operation C 7-bit address register (cannot be assigned a 10- bit address) C the first scl clock pulse in every data byte is stretched until the mcu has finished processing the previously received byte C bus error detection C optional general call detection C operates optionally as bus monitor without inter- fering in any way with bus traffic C setup time for any first transmitted data bit can be adjusted
171/268 - four-channel i 2 c bus interface (i2c) i 2 c bus interface (contd) 8.9.2 general description in addition to receiving and transmitting data, this interface convert them from serial to parallel for- mat and vice versa. the interface is connected, through a multiplexer, to one i 2 c bus among 4 by a data pin, sdax, and by a clock pin, sclx, where x range value is 1 to 4. it can be connected both with a standard i 2 c bus and a fast i 2 c bus. this selection is made by soft- ware. 8.9.2.1 mode selection the interface can operate in the four following modes: C slave transmitter/receiver C master transmitter/receiver by default, it operates in slave mode. the interface automatically switches from inactive slave to master after it generates a start condi- tion and from master to inactive slave in case of ar- bitration loss or a stop generation, this allows multi-master capability. 8.9.2.2 communication flow in master mode, it initiates a data transfer and generates the clock signal. a serial data transfer always begins with a start condition and ends with a stop condition. start condition is automatically generated by the interface when the data register is loaded by the slave address (see register de- scription for further details). stop condition is gen- erated in master mode by writing by software in the control register. in slave mode, the interface is capable of recog- nising its own address (7-bit), and the general call address. the general call address detection may be enabled or disabled by software. data and addresses are transferred as 8-bit bytes, msb first. the first byte following the start condi- tion is the address byte; it is always transmitted in master mode. a 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. refer to fig- ure 69 . the acknowledge may be enabled and disabled by software. the speed of the i 2 c interface may be selected between standard (15.625 - 100 khz), fast i 2 c (100- 400 khz), or extended i 2 c (500 - 800 khz). figure 69. i 2 c bus protocol scl sda 12 8 9 msb ack stop start condition condition vr02119b
172/268 - four-channel i 2 c bus interface (i2c) i 2 c bus interface (contd) 8.9.3 functional description refer to section 8.9.6 for the bit definitions. figure 70 gives the block diagram of the cell. by default, the i 2 c interface is in inactive slave mode, except when it initiates a transmit or receive sequence. after the microcontroller power-on reset state, the i 2 c interface is in reset state until the clear bit (i2cctr register) is reset. 8.9.3.1 configuring the interface before using the i 2 c interface, configure it as fol- lows. if it is to be used in slave mode, write the address assigned to the interface in the i2coar register. if it is to be used in master mode, write the scl clock frequency in the i2cfqr register. then, select one of the four buses available and configure the corresponding pins to the alternate function (refer to the i/o port chapter). depending on your application, you may use the advanced features (see the unproc and unexp bits of the i2cstr2 register) by setting the afen bit of the i2cctr register. you may also optionally set the rsrt and stop bits of the i2cctr register. you can enable the interrupt on stop condition and the spike filter by setting the iscen and sfen bits of the i2cstr1 register. if you want to use the monitor feature, then set the monitor bit in the i2cctr register. in all cases reset the clear bit of the i2cctr register to enable the i 2 c interface. figure 70. i2c interface block diagram data register (i2cdr) own address register (i2coar) frequency register (i2cfqr) status register 1 (i2cstr1) control register (i2cctr) sda in scl in interrupt status register 2 (i2cstr2) cpu interrupt clock start & stop scl 1 sda 1 input / output stage scl 2 sda 2 scl 3 sda 3 scl 4 sda 4 generation unit detection unit unit start & stop generation comparator address register shift data unit bit transfer state machine error and arbitration unit spike filter enable bus selection fast mode enable scl out acknowledge bit sda out error flags freq. selection
173/268 - four-channel i 2 c bus interface (i2c) i 2 c bus interface (contd) 8.9.3.2 slave mode as soon as a start condition is detected, the ad- dress is received from the sda line and sent to the shift register; then it is compared with: C the 7 msb of the interface address (see i2coar register) if the adr0 bit = 0 C the 4 msb of the interface address (see i2coar register) if the adr0 bit = 1 C the general call address address not matched : the interface ignores it and waits for another start condition. address matched : the interface generates in se- quence: C acknowledge pulse if the genc_ack bit (i2cctr register) is set and a general call is de- tected, or if the send_ack bit (i2cctr register) is reset and normal address if detected. C an interrupt is generated and the int bit of the i2cstr2 register is set. then check the i2cstr1 register to know the in- terface status: C read the first bit of the i2cstr1 register to know whether the byte stored in the i2cdr reg- ister is the address (first byte transferred in an i2c transaction) or a data. C if the gen_call bit is set, a general call has been requested by a master. C if the act_slv bit is set and the read bit is set, the interface is an active slave transmitter, else, if the act_slv bit is set and the read bit is re- set, the interface is an active slave receiver. slave receiver after the address, the slave receives bytes from the sda line into the i2cdr register via the inter- nal shift register. after each received byte the in- terface generates in sequence: C acknowledge pulse according to the send_ack bit value C an interrupt is generated and the int bit of the i2cstr2 register is set. using the first bit of the i2cstr1 register, you know whether the byte stored in the i2cdr regis- ter is the address (first byte transferred in an i2c transaction) or data. slave transmitter following the address reception, the slave sends bytes from the dr register to the sda line via the internal shift register. the slave writes in the i2cdr register the data to send on the sda bus. when the acknowledge pulse is received: C an interrupt is generated and the int bit of the i2cstr2 register is set. then you need to check the ack_bit of the i2cstr2 register to know whether the last byte has been acknowledged or not. if some data have to be sent again, write the value in the osddr register. closing a slave communication the i2c interface returns to inactive slave state as soon as a stop condition has been detected. if the iscen bit of the i2cstr2 is set, an interrupt is generated on detecting the stop condition, al- lowing the user to know if the transaction was suc- cessful by checking the error and active flags of the i2cstr1 register. 8.9.3.3 master mode to switch from default inactive slave mode to mas- ter mode: load a slave address in the i2cdr reg- ister. if the bus is free (active bit of the i2cstr2 reg- ister reset), then the i 2 c interface automatically generates a start condition followed by the i2cdr byte. then, on the 9th clock pulse, an interrupt is gener- ated and the int bit of the i2cstr2 register is set. check the ack_bit bit of the i2cstr1 register to know whether the slave address has been ac- knowledged or not, in order to manage the trans- action. if needed, generate a stop condition on the bus with the stop bit of the i2cstr1 register. note : if the rsrt bit of the i2cctr register is set, the master will generate a repeated start se- quence as soon as a new byte is loaded in the i2cdr register.
174/268 - four-channel i 2 c bus interface (i2c) i 2 c bus interface (contd) master receiver following the address transmission and acknowl- edgment, the master receives bytes from the sda line into the i2cdr register via the internal shift register. after each byte the interface generates in sequence: C acknowledge pulse according to the send_ack bit value, C an interrupt is generated and the int bit of the i2cstr2 register is set. then read the i2cdr register to store the trans- mitted data. note: in order to generate the non-acknowledge pulse after the last received data byte, the send_ack bit must be set just before reading the second last data byte. master transmitter following the address transmission and acknowl- edgment, the master sends bytes from the i2cdr register to the sda line via the internal shift regis- ter. when the acknowledge bit is received, the inter- face generates an interrupt and sets the int bit of the i2cstr2 register. the user can check the ack_bit bit of the i2cstr1 register in order to handle the transac- tion properly. closing a master communication the master interface will generate a stop condition on the bus when the user sets the stop bit of the i2cstr1 register. 8.9.4 interrupt handling to acknowledge interrupts generated by the i2c interface, software must write any value in the i2cdr register before leaving the i2c interrupt subroutine. this is necessary in all modes includ- ing slave or master receiver mode. 8.9.5 error cases each time an error occurs, an interrupt is generat- ed. then by checking the following bits, the user can identify the problem: C if the error bit in the i2cstr1 register is set, an illegal start or stop condition has been detect- ed. if the afen bit in the i2cctr register is set, the unproc, unexp, and misp bits of the i2cstr2 register indicate what kind of illegal condition has been detected. C if the arb_lost bit, in the i2cstr1 register is set, an arbitration lost occurred on the bus. note : the error bit has higher priority than the arb_lost bit, so if error is set, arb_lost has to be ignored.
175/268 - four-channel i 2 c bus interface (i2c) i 2 c bus interface (contd) 8.9.6 register description own address register (i2coar) r240 - read/write register page: 44 reset value: 0000 0000(00h) bit 7:1 = adr[7:1] interface slave address these bits are the 7 most significant bits of the 8- bit address assigned to interface when it works in slave mode. bit 0 = adr0 address match bit this bit selects when the i 2 c interface becomes active if it works in slave mode, and if its slave ad- dress is transmitted on the bus. 0: the interface becomes an active slave when the 7 most significant bits adr[7:1] match the ad- dress transmitted by a master. 1: the interface becomes an active slave when only the 4 most significant bits adr[7:4] match the address transmitted by a master. this fea- ture allows the master to send data simultane- ously to up to 8 slaves with identical adr(7:4). 70 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0
176/268 - four-channel i 2 c bus interface (i2c) i 2 c bus interface (contd) frequency register (i2cfqr) r241 - read/write register page: 44 reset value: 0000 0000(00h) bits 7:6 = bus_s[1:0] i 2 c bus selection bits these bits connect the i 2 c interface to one of the four possible buses as described in table 35 . table 35. i 2 c bus selection bit 5 = fmen fast mode enable bit this bit enables or disables the fast mode for the scl bus frequency. 0: standard mode (up to 100 khz). 1: fast mode (over 100 khz) bit 4 = pp_drv push-pull drive mode bit this bit determines if the master drives the scl/ sda buses in push-pull mode or in normal mode. this allows the master to send data to the slave at a faster speed. 0: the push-pull drive mode is disabled 1: the push-pull drive mode is enabled. all nor- mal bus frequencies are doubled with the only exception that the push-pull drive mode is auto- matically disabled when q[3:0]=1110 or q[3:0]=1111 to yield an scl frequency of 500 khz or 800 khz. refer to q[3:0] bit description. note : the master automatically switches tempo- rarily to normal bus driving mode with active pull- up disabled and scl frequency reduced by factor of 2 when receiving acknowledges or data from the addressed slave. bit 3:0 = q[3:0] scl clock frequency bits these bits select the scl clock frequency when the interface works in master mode. in slave trans- mitter mode, they can be used to adjust the setting up time between the first data byte and the clock. refer to table 36 . in push-pull mode, the frequency values present- ed in the following table correspond to an approxi- mate frequency assuming that : C the first data bit is transferred at a lower frequen- cy (clock stretching capability), C the acknowledge bit is transferred at the slave speed without push-pull mode, C other data bits are transferred with a real period 250 ns shorter than the values indicated in this table. using the spike filter will add an internal delay act- ing as a period increase by 250-ns steps. table 36. scl clock frequency selection * these values are not covered by the philips i 2 c specification notes : C the maximum allowed frequency depends on the state of the fmen control bit (if pp_drv=0, standard mode: 100 khz; fast mode: 666.6 khz) C all frequency values depend on the bus line load (except push-pull mode). C all above values are obtained with loads corre- sponding to a rise time from 0 to 250 ns. C any higher rise time (especially in standard mode) will increase the period of the bus line fre- quency by 250-ns steps. 70 bus_s0 bus_s1 fmen pp_drv q3 q2 q1 q0 bus_s1 bus_s0 selected bus 0 0 scl1/sda1 0 1 scl2/sda2 1 0 scl3/sda3 1 1 scl4/sda4 scl bus frequency (in khz) q[3:0] pp_drv = 0 scl max frequency pp_drv = 1 scl frequency (khz) (period: +0/-250ns 0000 20.10 40.40 0001 30.53 61.54 0010 40.40 81.63 0011 50.63 102.56 0100 63.49 129.03 0101 72.73 148.15 0110 85.11 173.91 0111 102.56 210.53 1000 129.03 266.67 1001 173.91 363.64 1010 210.53 444.44 1011 266.67 444.44 1100 400.00 571.43 1101 444.44 666.67 1110 444.44 * 666.67 1111 666.67 * 666.67
177/268 - four-channel i 2 c bus interface (i2c) i 2 c bus interface (contd) control register (i2cctr) r242 - read/write register page: 44 reset value: 0000 0001(01h) bit 7 = afen advanced features enable bit this bit enables or disables the unexpected & un- processed error detection. refer to the description of the unproc and unexp bits in the i2cstr2 register. 0: advanced features disabled 1: advanced features enabled bit 6 = rti return to inactive state bit this bit determines the interface status after an in- terrupt is processed (either after a complete trans- fer or an error occured). 0: the interface keeps its active state 1: the interface (master or slave) returns to the in- active slave state note : the state of the active flag (i2cstr1.0) is maintained.the rti bit is automatically cleared. bit 5 = genc_ack general call acknowledge bit this bit determines the response of the i 2 c inter- face when a general call is detected on the bus. 0: the interface will acknowledge the reception of a general call immediately after receiving the address 00h. an interrupt is generated at the end of the acknowledge interval that follows the address. 1: the interface will not acknowledge a general call and does not generate an interrupt, i.e. the interface will remain an inactive slave. bit 4 = send_ack send acknowledge bit this bit is set by software to define if the acknowl- edge bit is placed on the bus when the interface is operating as a master receiver, active slave re- ceiver or an active slave. 0: an inactive interface will acknowledge the re- ception of its address and switch to active slave mode. 1: the interface will not acknowledge the reception of its address and remains inactive. note: the interface operating as a master slave receiver is free to acknowledge or not all data bytes. in a normal i 2 c transaction, it acknowledg- es all data bytes except the last received from a slave/master transmitter. send_ack should be programmed before receiv- ing the relevant byte (data or address). bit 3 = monitor bus monitor mode bit this bit determines if the interface acts as a bus monitor or not. 0: the bus monitor mode is disabled. 1: the interface behaves as a bus monitor. the in- terface becomes a slave regardless of the ad- dress received, but neither the address or the following data is acknowledged (this is equiva- lent to send_ack=1). if a read address is re- ceived, the high state of the least significant bit of this address is suppressed inside the inter- face and all data bytes are processed by the mcu as received data. bit 2 = rsrt repeated start bit this bit determines if the interface generates auto- matically a repeated start condition on the i 2 c bus (in master mode) as soon as a new byte is ready to be send. 0: repeated start disabled 1: repeated start enabled note : this bit is automatically cleared. bit 1 = stop stop condition generation bit when working in master mode, this bit enables or disables a stop condition generation on the i 2 c bus. 0: no stop condition is generated 1: the master will generate a stop condition to ter- minate the bus transaction. the master will au- tomatically revert to an inactive slave and the stop bit will be cleared. bit 0 = clear clear interface bit this bit enables or disables the i 2 c interface. 0: the interface is enabled 1: a general reset is generated. the interface be- comes an inactive slave and the scl and sda buses drive signals are removed. the system is kept in reset state until the clear bit is writ- ten to 0. note : the clear bit is 1 (i.e. the interface is dis- abled) when exiting from the mcus power-on re- set state. 70 afen rti genc_ ack send_ ack moni tor rsrt stop clear
178/268 - four-channel i 2 c bus interface (i2c) i 2 c bus interface (contd) data register (i2cdr) r243 - read/write register page: 44 reset value: 0000 0000(00h) bit 7:0 = sr[8:1] address or data byte these bits contains the address or data byte load- ed by software for sending on the i 2 c bus, and also the address or data byte received on the bus to be read by software. when read, this register reflects the last byte which has been transferred on the bus. reading this register is equivalent to reading the shift regis- ter of the interface. when written, the contents of this register will be transferred into the shift register of the interface. status register 2 (i2cstr2) r244 - read/write (bit 7:6),read only (bit 5:0) register page: 44 reset value: 0000 0000(00h) bit 7 = iscen interrupt on stop condition enable bit this bit determines if an interrupt is generated as soon as a stop condition has been detected on the bus. 0: no interrupt generated on a bus stop condition 1: an interrupt is generated on a bus stop condi- tion. note : when the interface is involved in a transac- tion, checking the error status flag related to the error detection allows to determine if the trans- action has been successfully completed. this in- terrupt can be useful for an interface waiting for a bus free condition in order to become a master as soon as possible. checking the active bit (in the i2cstr1 register) allows to correctly identify an interrupt generated by a stop condition. bit 6 = sfen spike filter enable bit this bit enables or disables the spike filters on the sdax and sclx inputs (x is 1 to 4). 0: spike filters disabled 1: spike filters enabled note : the length of a pulse identified as a spike depends on the cpuclk frequency used (cpu- clk frequencies from 10 to 20 mhz allow to filter pulses smaller than 100 to 40 ns). bit 5 = sclin scl input status bit this read-only bit describes the current logic state on the scl bus. it can be used to sample the signal on a newly se- lected scl bus for a quick determination concern- ing the bus use and the bus clock frequency. bit 4 = sdain sda input status bit this read-only bit describes the current logic state on the sda bus. it can be used to sample the signal on a newly se- lected sda bus for a quick determination of the state of this bus, prior starting a transaction. bit 3 = int interrupt status bit this (read-only) bit indicates if an event has oc- curred. 0: no interrupt requested or an interrupt resulting from a stop condition occurred. 1: the interface enters an interrupt state resulting from any error (bus error or arbitration loss) or any byte transfer completed. bit 2 = unproc unprocessed flag bit this bit is useful in a multimaster mode system, to solve conflicts between a repeated start or a stop condition and any bit of an address or data byte from other concurrent masters. 0: no error occurred. 1: a master interface tried to generate a repeat- ed start or a stop condition, which never oc- curred. note : if this bit is set, it will automatically activate the error bit. note : this bit is only valid when the advanced features enable bit afen is set in the i2cctr register. 70 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 70 iscen sfen sclin sdain int unproc unexp misp
179/268 - four-channel i 2 c bus interface (i2c) i 2 c bus interface (contd) bit 1 = unexp unexpected flag bit this bit is useful for error detection in a multimas- ter mode system, when a master is continuing its transaction while an other concurrent master wants to finish or restart a transaction by sending a start or a stop condition. together with the misp bit, it covers all possible cases, where unexpected start or stop condi- tions occur, while the interface is a master. 0: no unexpected error detected 1: a master interface receives a start or a stop condition, while sending the first bit of a data byte. notes : C if this bit is set, it will automatically activate the error bit. C this bit is only valid when the advanced fea- tures enable bit afen is set. bit 0 = misp misplaced flag bit this bit indicates if the interface has received a misplaced start or stop condition during ad- dress transfer or any data byte transfer (besides first data bit). this error detection is also activated during the acknowledge bit transfer. together with the unexp bit, it covers all possible cases, where unexpected start or stop condi- tions occur, while the interface is a master. 0: no misplaced start or stop condition has been detected 1: a misplaced start or stop condition has been received. note : if this bit is set, it will automatically activate the error bit. status register 1 (i2cstr1) r245 - read only register page: 44 reset value: 0000 0000(00h) bit 7 = error error detection bit this bit indicates if an error occurred on the bus or not. 0: no error detected 1: an error is detected. it is an illegal start or stop condition, i.e. a signal level transition occurs on the sda bus during presence of a clock pulse on the scl bus. an interrupt is generated in this case. the inter- face stays in the error state until the error flag is reset by either a clear operation, a stop re- quest or a return to inactive state operation. note : the error bit has higher priority than the arb_lost bit (i.e. when error=1, the value of arb_lost has to be ignored). 70 error arb_ lost read first gen_ call ack_ bit act_ slv active
180/268 - four-channel i 2 c bus interface (i2c) i 2 c bus interface (contd) bit 6 = arb_lost arbitration lost detection bit this bit indicates if an arbitration lost occurred on the bus. 0: no arbitration lost occurred 1: an arbitration lost occurred. the bit is set when the interface operating as a master loses arbi- tration to another master on the bus. if a loss of arbitration occurs during the address byte and if the interface has been addressed by the winning master (act_slv=1), then the arb_lost flag is cleared by any data load operation into i2cdr. in all other cases it is up to the user to return the interface into the status of an inactive slave via either a clear operation, a return to in- active state operation or a stop request. if a loss of arbitration occurs, an interrupt is generated: when occurring during the address byte, the interrupt is generated at the end of the acknowledge bit; when occurring during a data byte, the interrupt is generated immediately. note : the error bit has higher priority than the arb_lost bit (i.e. when error=1, the value of arb_lost has to be ignored). bit 5 = read read/write status bit this flag represents the state of the read/write bit of the address byte. it is updated either for a mas- ter or an active slave after the end of the address byte. it is cleared, when the interface returns to the inactive slave status (i.e. after the normal comple- tion of a transaction, when exiting from any error state, ...). 0: write operation 1: read operation bit 4 = first transmission status bit this bit indicates if the byte transmitted on the bus is an address byte or a data byte. 0: the byte is a data byte 1: the byte is the address part of an i 2 c bus trans- action. note : the first bit is automatically cleared at the end of the interrupt, after the address, and when the interface returns into inactive slave state. bit 3 = gen_call general call status bit this bit indicates if a general call has been detect- ed on the bus. this bit is updated only if genc_ack=0 (see i2cctr register for more details) 0: no general call detected, or genc_ack=1. 1: the general call address 00h has been recog- nized by the slave. note : this bit is cleared by hardware when the in- terface returns to the inactive slave status. bit 2 = ack_bit acknowledge bit this bit reflects the logic level of the acknowledge bit detected at the end of the last byte (either ad- dress or data) transmitted on the i 2 c bus. it re- mains valid until the interface exits from the inter- rupt state. 0: acknowledge detected 1: no acknowledge detected bit 1 = act_slv active slave status bit this bit indicates the slave status of the interface. 0: the interface is not working in slave mode. it may be inactive or in master mode (see the active bit for more details). 1: the address assigned to the interface has been received on the bus and has been acknowl- edged by the interface (send_ack=0). note : this bit is cleared when the interface returns into inactive slave state. bit 0 = active interface activity status bit this bit indicates if the interface is active or not. 0: the i 2 c interface is inactive 1: the interface is active. the bit is set throughout the interval between a start condition and the first stop condition that follows on the i 2 c bus. note : it is reset by the clear bit.
181/268 - four-channel i 2 c bus interface (i2c) i 2 c bus interface (contd) table 37. i2c interface register map and reset values address register name 7 6 5 4 3210 240 i2coar reset value adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 241 i2cfqr reset value bus_s0 bus_s1 fmen pp_drv q3 q2 q1 q0 242 i2cctr reset value afen rti genc_ack send_ack monitor rsrt stop clear 243 i2cdr reset value sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 244 i2cstr2 reset value iscen sfen sclin sdain int unproc unexp misp 245 i2cstr1 reset value error arb_lost read first gen_ call ack_bit act_slv active
182/268 - serial peripheral interface (spi) 8.10 serial peripheral interface (spi) 8.10.1 introduction the serial peripheral interface (spi) is a general purpose on-chip shift register peripheral. it allows communication with external peripherals via an spi protocol bus. in addition, special operating modes allow re- duced software overhead when implementing i 2 c- bus and im-bus communication standards. the spi uses up to 3 pins: serial data in (sdi), serial data out (sdo) and synchronous serial clock (sck). additional i/o pins may act as device selects or im-bus address identifier signals. the main features are: n full duplex synchronous transfer if 3 i/o pins are used n master operation only n 4 programmable bit rates n programmable clock polarity and phase n busy flag n end of transmission interrupt n additional hardware to facilitate more complex protocols 8.10.2 device-specific options depending on the st9 variant and package type, the spi interface signals may not be connected to separate external pins. refer to the peripheral configuration chapter for the device pin-out. figure 71. block diagram n read buffer serial peripheral interface data register ( spidr ) polarity phase baud rate multiplexer st9 interrupt transmission end of spen bms arb busy cpol cpha spr1 spr0 data bus r254 intclk serial peripheral control register ( spicr ) r253 sdo sdi sck/int2 vr000347 10 int2 internal serial clock to mspi control logic i n t 2 intb0 * * common for transmit and receive
183/268 - serial peripheral interface (spi) serial peripheral interface (contd) 8.10.3 functional description the spi, when enabled, receives input data from the internal data bus to the spi data register (spidr). a serial clock (sck) is generated by controlling through software two bits in the spi control register (spicr). the data is parallel loaded into the 8 bit shift register during a write cy- cle. this is shifted out serially via the sdo pin, msb first, to the slave device, which responds by sending its data to the master device via the sdi pin. this implies full duplex transmission if 3 i/o pins are used with both the data-out and data-in synchronized with the same clock signal, sck. thus the transmitted byte is replaced by the re- ceived byte, eliminating the need for separate tx empty and rx full status bits. when the shift register is loaded, data is parallel transferred to the read buffer and becomes availa- ble to the cpu during a subsequent read cycle. the spi requires three i/o port pins: sck serial clock signal sdo serial data out sdi serial data in an additional i/o port output bit may be used as a slave chip select signal. data and clock pins i2c bus protocol are open-drain to allow arbitration and multiplexing. figure 72 below shows a typical spi network. figure 72. a typical spi network n 8.10.3.1 input signal description serial data in (sdi) data is transferred serially from a slave to a mas- ter on this line, most significant bit first. in an s- bus/i 2 c-bus configuration, the sdi line senses the value forced on the data line (by sdo or by an- other peripheral connected to the s-bus/i 2 c-bus). 8.10.3.2 output signal description serial data out (sdo) the sdo pin is configured as an output for the master device. this is obtained by programming the corresponding i/o pin as an output alternate function. data is transferred serially from a master to a slave on sdo, most significant bit first. the master device always allows data to be applied on the sdo line one half cycle before the clock edge, in order to latch the data for the slave device. the sdo pin is forced to high impedance when the spi is disabled. during an s-bus or i 2 c-bus protocol, when arbi- tration is lost, sdo is set to one (thus not driving the line, as sdo is configured as an open drain). master serial clock (sck) the master device uses sck to latch the incoming data on the sdi line. this pin is forced to a high im- pedance state when spi is disabled (spen, spicr.7 = 0), in order to avoid clock contention from different masters in a multi-master system. the master device generates the sck clock from intclk. the sck clock is used to synchronize data transfer, both in to and out of the device, through its sdi and sdo pins. the sck clock type, and its relationship with data is controlled by the cpol (clock polarity) and cpha (clock phase) bits in the serial peripheral control regis- ter (spicr). this input is provided with a digital fil- ter which eliminates spikes lasting less than one intclk period. two bits, spr1 and spr0, in the serial peripheral control register (spicr), select the clock rate. four frequencies can be selected, two in the high frequency range (mostly used with the spi proto- col) and two in the medium frequency range (mostly used with more complex protocols).
184/268 - serial peripheral interface (spi) serial peripheral interface (contd) figure 73. spi i/o pins n 8.10.4 interrupt structure the spi peripheral is associated with external in- terrupt channel b0 (pin int2). multiplexing be- tween the external pin and the spi internal source is controlled by the spen and bms bits, as shown in table 38 . the two possible spi interrupt sources are: C end of transmission (after each byte). C s-bus/i 2 c-bus start or stop condition. care should be taken when toggling the spen and/or bms bits from the 0,0 condition. before changing the interrupt source from the external pin to the internal function, the b0 interrupt channel should be masked. eimr.2 (external interrupt mask register, bit 2, imbo) and eipr.2 (external interrupt pending register bit 2, imp0) should be 0 before changing the source. this sequence of events is to avoid the generating and reading of spurious interrupts. a delay instruction lasting at least 4 clock cycles (e.g. 2 nops) should be inserted between the spen toggle instruction and the interrupt pending bit reset instruction. the int2 input function is always mapped togeth- er with the sck input function, to allow start/stop bit detection when using s-bus/i 2 c-bus protocols. a start condition occurs when sdi goes from 1 to 0 and sck is 1. the stop condition occurs when sdi goes from 0 to 1 and sck is 1. for both stop and start conditions, spen = 0 and bms = 1. table 38. interrupt configuration spi data bus port latch sdi sck int2 sdo sck sdo sdi int2 bit port latch bit port latch bit spen bms interrupt source 0 0 external channel int2 0 1 s-bus/i 2 c bus start or stop condition 1 x end of a byte transmission
185/268 - serial peripheral interface (spi) serial peripheral interface (contd) 8.10.5 working with other protocols the spi peripheral offers the following facilities for operation with s-bus/i 2 c-bus and im-bus proto- cols: n interrupt request on start/stop detection n hardware clock synchronisation n arbitration lost flag with an automatic set of data line note that the i/o bit associated with the spi should be returned to a defined state as a normal i/o pin before changing the spi protocol. the following paragraphs provide information on how to manage these protocols. 8.10.6 i 2 c-bus interface the i 2 c-bus is a two-wire bidirectional data-bus, the two lines being sda (serial data) and scl (serial clock). both are open drain lines, to allow arbitration. as shown in figure 75 , data is toggled with clock low. an i2c bus start condition is the transition on sdi from 1 to 0 with the sck held high. in a stop condition, the sck is also high and the transition on sdi is from 0 to 1. during both of these conditions, if spen = 0 and bms = 1 then an interrupt request is performed. each transmission consists of nine clock pulses (scl line). the first 8 pulses transmit the byte (msb first), the ninth pulse is used by the receiver to acknowledge. figure 74. s-bus / i 2 c-bus peripheral compatibility without s-bus chip select
186/268 - serial peripheral interface (spi) serial peripheral interface (contd) table 39. typical i 2 c-bus sequences figure 75. spi data and clock timing (for i2c protocol) n phase software hardware notes initialize spicr.cpol, cpha = 0, 0 spicr.spen = 0 spicr.bms = 1 sck pin set as af output sdi pin set as input set sdo port bit to 1 sck, sdo in hi-z scl, sda = 1, 1 set polarity and phase spi disable start/stop interrupt enable start sdo pin set as output open drain set sdo port bit to 0 sda = 0, scl = 1 interrupt request start condition receiver start detection transmission spicr.spen = 1 sdo pin as alternate func- tion output load data into spidr scl = 0 start transmission interrupt request at end of byte transmission managed by interrupt rou- tine load ffh when receiv- ing end of transmission detection acknowledge spicr.spen = 0 poll sda line set sda line spicr.spen = 1 sck, sdo in hi-z scl, sda = 1 scl = 0 spi disable only if transmitting only if receiving only if transmitting stop sdo pin set as output open drain spicr.spen = 0 set sdo port bit to 1 sda = 1 interrupt request stop condition sda scl start condition 12 8 9 1st byte ack clock pulse for acknowledgement driven by software 12 89 driven by sw for acknowledgement clock pulse condition stop ack n byte th vr000188
187/268 - serial peripheral interface (spi) serial peripheral interface (contd) the data on the sda line is sampled on the low to high transition of the scl line. spi working with an i 2 c-bus to use the spi with the i 2 c-bus protocol, the sck line is used as scl; the sdi and sdo lines, exter- nally wire-ored, are used as sda. all output pins must be configured as open drain (see figure 74 ). figure 39 illustrates the typical i 2 c-bus sequence, comprising 5 phases: initialization, start, trans- mission, acknowledge and stop. it should be not- ed that only the first 8 bits are handled by the spi peripheral; the acknowledge bit must be man- aged by software, by polling or forcing the scl and sdo lines via the corresponding i/o port bits. during the transmission phase, the following i 2 c- bus features are also supported by hardware. clock synchronization in a multimaster i 2 c-bus system, when several masters generate their own clock, synchronization is required. the first master which releases the scl line stops internal counting, restarting only when the scl line goes high (released by all the other masters). in this manner, devices using dif- ferent clock sources and different frequencies can be interfaced. arbitration lost when several masters are sending data on the sda line, the following takes place: if the transmit- ter sends a 1 and the sda line is forced low by another device, the arb flag (spicr.5) is set and the sdo buffer is disabled (arb is reset and the sdo buffer is enabled when spidr is written to again). when bms is set, the peripheral clock is supplied through the int2 line by the external clock line (scl). due to potential noise spikes (which must last longer than one intclk period to be detected), rx or tx may gain a clock pulse. referring to figure 76 , if device st9-1 detects a noise spike and therefore gains a clock pulse, it will stop its transmission early and hold the clock line low, causing device st9-2 to freeze on the 7th bit. to exit and recover from this condition, the bms bit must be reset; this will cause the spi logic to be reset, thus aborting the current transmission. an end of transmission interrupt is generated fol- lowing this reset sequence. figure 76. spi arbitration n n internal serial clock bhs 0 1 st9-1 sck mspi logic control int 2 mspi control logic 0 1 bhs sck internal serial clock st9-2 int 2 1234567 st9-2-sck st9-1-sck 8 7 6 5 3 2 1 4 spike vr001410
188/268 - serial peripheral interface (spi) serial peripheral interface (contd) 8.10.7 s-bus interface the s-bus is a three-wire bidirectional data-bus, possessing functional features similar to the i 2 c- bus. as opposed to the i 2 c-bus, the start/stop conditions are determined by encoding the infor- mation on 3 wires rather than on 2, as shown in figure 78 . the additional line is referred as sen. spi working with s-bus the s-bus protocol uses the same pin configura- tion as the i 2 c-bus for generating the scl and sda lines. the additional sen line is managed through a standard st9 i/o port line, under soft- ware control (see figure 74 ). figure 77. mixed s-bus and i 2 c-bus system n figure 78. s-bus configuration n 12 3 4 56 start stop va00440 scl sda sen
189/268 - serial peripheral interface (spi) serial peripheral interface (contd) 8.10.8 im-bus interface the im-bus features a bidirectional data line and a clock line; in addition, it requires an ident line to distinguish an address byte from a data byte ( fig- ure 80 ). unlike the i 2 c-bus protocol, the im-bus protocol sends the least significant bit first; this re- quires a software routine which reverses the bit or- der before sending, and after receiving, a data byte. figure 79 shows the connections between an im-bus peripheral and an st9 spi. the sdo and sdi pins are connected to the bidirectional data pin of the peripheral device. the sdo alter- nate function is configured as open-drain (exter- nal 2.5k w pull-up resistors are required). with this type of configuration, data is sent to the peripheral by writing the data byte to the spidr register. to receive data from the peripheral, the user should write ffh to the spidr register, in or- der to generate the shift clock pulses. as the sdo line is set to the open-drain configuration, the in- coming data bits that are set to 1 do not affect the sdo/sdi line status (which defaults to a high level due to the ffh value in the transmit register), while incoming bits that are set to 0 pull the input line low. in software it is necessary to initialise the st9 spi by setting both cpol and cpha to 1. by using a general purpose i/o as the ident line, and forcing it to a logical 0 when writing to the spidr regis- ter, an address is sent (or read). then, by setting this bit to 1 and writing to spidr, data is sent to the peripheral. when all the address and data pairs are sent, it is necessary to drive the ident line low and high to create a short pulse. this will generate the stop condition. figure 79. st9 and im-bus peripheral n figure 80. im bus timing v dd sck sdi sdo st9 mcu im-bus clock data ident im-bus slave device protocol portx vr001427 2.5 k 2x 1 2 3 45 6 clock line data line 1 2 4 3 5 6 msb vr000172 msb lsb lsb ident
190/268 - serial peripheral interface (spi) serial peripheral interface (contd) 8.10.9 register description it is possible to have up to 3 independent spis in the same device (refer to the device block dia- gram). in this case they are named spi0 thru spi2. if the device has one spi converter it uses the register adresses of spi0. the register map is the following: note: in the register description on the following pages, register and page numbers are given using the example of spi0. spi data register (spidr) r253 - read/write register page: 0 reset value: undefined bit 7:0 = d[0:7] : spi data . this register contains the data transmitted and re- ceived by the spi. data is transmitted bit 7 first, and incoming data is received into bit 0. transmis- sion is started by writing to this register. note: spidr state remains undefined until the end of transmission of the first byte. spi control register (spicr) r254 - read/write register page: 0 reset value: 0000 0000 (00h) bit 7 = spen : serial peripheral enable . 0: sck and sdo are kept tristate. 1: both alternate functions sck and sdo are ena- bled. note: furthermore, spen (together with the bms bit) affects the selection of the source for interrupt channel b0. transmission starts when data is writ- ten to the spidr register. bit 6 = bms : s-bus/i 2 c-bus mode selector . 0: perform a re-initialisation of the spi logic, thus allowing recovery procedures after a rx/tx fail- ure. 1: enable s-bus/i 2 c-bus arbitration, clock synchro- nization and start/ stop detection (spi used in an s-bus/i 2 c-bus protocol). note: when the bms bit is reset, it affects (togeth- er with the spen bit) the selection of the source for interrupt channel b0. bit 5 = arb : arbitration flag bit. this bit is set by hardware and can be reset by software. 0: s-bus/i 2 c-bus stop condition is detected. 1: arbitration lost by the spi in s-bus/i 2 c-bus mode. note: when arb is set automatically, the sdo pin is set to a high value until a write instruction on spidr is performed. bit 4 = busy : spi busy flag . this bit is set by hardware. it allows the user to monitor the spi status by polling its value. 0: no transmission in progress. 1: transmission in progress. bit 3 = cpol : transmission clock polarity . cpol controls the normal or steady state value of the clock when data is not being transferred. please refer to the following table and to figure 81 to see this bit action (together with the cpha bit). note: as the sck line is held in a high impedance state when the spi is disabled (spen = 0), the sck pin must be connected to v ss or to v cc through a resistor, depending on the cpol state. polarity should be set during the initialisation rou- tine, in accordance with the setting of all peripher- als, and should not be changed during program execution. register spin page spidr r253 spi0 0 spicr r254 spi0 0 spidr1 r253 spi1 7 spicr1 r254 spi1 7 spidr2 r245 spi2 7 spicr2 r246 spi2 7 70 d7 d6 d5 d4 d3 d2 d1 d0 70 spen bms arb busy cpol cpha spr1 spr0
191/268 - serial peripheral interface (spi) serial peripheral interface (contd) bit 2 = cpha : transmission clock phase. cpha controls the relationship between the data on the sdi and sdo pins, and the clock signal on the sck pin. the cpha bit selects the clock edge used to capture data. it has its greatest impact on the first bit transmitted (msb), because it does (or does not) allow a clock transition before the first data capture edge. figure 81 shows the relation- ship between cpha, cpol and sck, and indi- cates active clock edges and strobe times. bit 1:0 = spr[1:0]: spi rate. these two bits select one (of four) baud rates, to be used as sck. figure 81. spi data and clock timing cpol cpha sck (in figure 81 ) 0 0 1 1 0 1 0 1 (a) (b) (c) (d) spr1 spr0 clock divider sck frequency (@ intclk = 24mhz) 0 0 1 1 0 1 0 1 8 16 128 256 3000khz 1500khz 187.5khz 93.75khz (t = 0.33 m s) (t = 0.67 m s) (t = 5.33 m s) (t = 10.66 m s)
192/268 - serial communications interface (sci) 8.11 serial communications interface (sci) 8.11.1 introduction the serial communications interface (sci) offers full-duplex asynchronous serial data exchange for interfacing a wide range of external equipment. it has the following principal features: n full duplex asynchronous operation. n transmit, receive, line status, and device address interrupt generation. n integral baud rate generator capable of dividing the input clock by any value from 2 to 2 16 -1 (16 bit word) and generating the internal 16x data sampling clock for asynchronous operation. n fully programmable serial interface: C 5, 6, 7, or 8 bit word length. C even, odd, or no parity generation and detec- tion. C 0, 1, 1-1/2, 2, 2-1/2, 3 stop bit generation. C complete status reporting capabilities. C line break generation and detection. n programmable address indication bit (wake-up bit) and user invisible compare logic to support multiple microcomputer networking. optional character search function. n internal diagnostic capabilities: C local loopback for communications link fault isolation. C auto-echo for communications link fault isola- tion. n separate interrupt/dma channels for transmit and receive. figure 82. sci block diagram transmit buffer register register shift transmit register shift receiver register compare address register buffer receiver dma controller clock and baud rate generator st9 core bus sout sin frame control and status dma controller
193/268 - serial communications interface (sci) serial communications interface (contd) figure 83. sci functional schematic 8.11.2 sci operation e ach data bit is sampled 16 times per clock period. figure 84. sci operating modes 8.11.3 serial frame format characters sent or received by the sci can have some or all of the features in the following format, depending on the operating mode: start : the start bit indicates the beginning of a data frame. the start condition is detected as a high to low transition. data : the data word length is programmable from 5 to 8 bits. lsb are transmitted first. parity : the parity bit is optional, and can be used with any word length. it is used for error checking and is set so as to make the total number of high bits in data plus parity odd or even, de- pending on the number of 1s in the data field. address/9th : the address/9th bit is optional and may be added to any word format. it is used to indicate that the data is an address (bit set). the address/9th bit is useful when several mi- crocontrollers are exchanging data on the same serial bus. individual microcontrollers can stay idle on the serial bus, waiting for a transmitted ad- dress. when a microcontroller recognizes its own address, it can begin data reception, likewise, on the transmit side, the microcontroller can transmit another address to begin communication with a different microcontroller. the address/9th bit can be used as an addi- tional data bit or to mark control words (9th bit). stop : indicates the end of a data frame. the stop bit can be programmed to be 1, 1.5, 2, 2.5 or 3 bits long, depending on the mode. it returns the sci to the quiescent marking state (i.e., a con- stant high-state condition) which lasts until a new start bit indicates an incoming word. figure 85. sci character formats (1) lsb first rx shift register tx buffer register tx shift register aen rx buffer register baud rate generator intclk lben sout sin i/o clock start bit data parity stop bit 16 16 16 va00271 start data (1) parity address stop # bits 0, 1 5, 6, 7, 8 0, 1 0, 1 0, 1, 1.5, 2, 2.5 states none odd even on off
194/268 - serial communications interface (sci) serial communications interface (contd) 8.11.3.1 data transfer data to be transmitted by the sci is first loaded by the program into the transmitter buffer register. the sci will transfer the data into the transmitter shift register when the shift register becomes available (empty). the transmitter shift register converts the parallel data into serial format for transmission via the sci alternate function out- put, serial data out. on completion of the transfer, the transmitter buffer register interrupt pending bit will be updated. if the selected word length is less than 8 bits, the unused most significant bits do not need to be defined. incoming serial data from the serial data input pin is converted into parallel format by the receiver shift register. at the end of the input data frame, the valid data portion of the received word is trans- ferred from the receiver shift register into the re- ceiver buffer register. all receiver interrupt con- ditions are updated at the time of transfer. if the selected character format is less than 8 bits, the unused most significant bits will be set. the frame control and status block creates and checks the character configuration (data length and number of stop bits), as well as the source of the transmitter/receiver clock. the internal baud rate generator contains a pro- grammable divide by n counter which can be used to generate the clocks for the transmitter and/or receiver. the baud rate generator uses intclk as the clock source. the address bit/d9 is optional and may be added to any word. it is commonly used in network or ma- chine control applications. when enabled (ab set), an address or ninth data bit can be added to a transmitted word by setting the set address bit (sa). this is then appended to the next word en- tered into the (empty) transmitter buffer register and then cleared by hardware. on character input, a set address bit can indicate that the data pre- ceding the bit is an address which may be com- pared in hardware with the value in the address compare register (acr) to generate an address match interrupt when equal. the address bit and address comparison regis- ter can also be combined to generate four different types of address interrupt to suit different proto- cols, based on the status of the address mode en- able bit (amen) and the address mode bit (am) in the chcr register. the character match address interrupt mode may be used as a powerful character search mode, generating an interrupt on reception of a predeter- mined character e.g. carriage return or end of block codes (character match interrupt). the line break condition is fully supported for both transmission and reception. line break is sent by setting the sb bit (idpr). this causes the trans- mitter output to be held low (after all buffered data has been transmitted) for a minimum of one com- plete word length and until the sb bit is reset. testing of the communications channel may be performed using the built-in facilities of the sci pe- ripheral. auto-echo mode and loop-back mode may be used individually or together. table 40. address interrupt modes figure 86. auto echo configuration figure 87. loop back configuration figure 88. auto echo and loop-back configuration if 9th data bit is set if character match if character match and 9th data bit is set if character match immediately follows break receiver sin sout transmitter receiver sin sout transmitter logical 1 receiver sin sout transmitter
195/268 - serial communications interface (sci) serial communications interface (contd) 8.11.4 clocks and serial transmission rates the communication bit rate of the sci transmitter and receiver sections is provided from the internal baud rate generator divided by 16. x baud rate generator. the internal baud rate generator consists of a 16-bit programmable di- vide by n counter which can be used to generate the transmitter and/or receiver clocks. the mini- mum baud rate divisor is 2 and the maximum divi- sor is 2 16 -1. with intclk running at 20mhz or 10mhz, a max- imum bit rate of 625 kbaud or 312.5k baud re- spectively is possible. warning: programming the baud rate divider to 0 or 1 will stop the divider. the output of the baud rate generator has a pre- cise 50% duty cycle. intclk (and therefore the mcu xtal) should be chosen to provide a suitable frequency for division by the baud rate generator to give the required transmit and receive bit rates. suitable intclk frequencies and the respective divider values for standard baud rates are shown in table 41 . 8.11.5 sci initialization procedure writing to either of the two baud rate generator registers immediately disables and resets the sci baud rate generator, as well as the transmitter and receiver circuitry. after writing to the second baud rate generator register, the transmitter and receiver circuits are enabled. the baud rate generator will load the new value and start counting. to initialize the sci, the user should first initialize the most significant byte of the baud rate gener- ator register; this will reset all sci circuitry. the user should then initialize all other sci registers (sicr/socr included) for the desired operating mode and then, to enable the sci, he should ini- tialize the least significant byte baud rate gener- ator register. 'on-the-fly' modifications of the control registers' content during transmitter/receiver operations, al- though possible, can corrupt data and produce un- desirable spikes on the i/o lines. furthermore, modifying the control registers' content without reinitialising the sci circuitry (during stand-by cy- cles, waiting to transmit or receive data) must be kept carefully under control by software to avoid spurious data being transmitted or received.
196/268 - serial communications interface (sci) serial communications interface (contd) table 41. practical example of sci baud rate generator divider values figure 89. sci baud rate generator initialization sequence intclk: 19660.800 khz baud rate clock factor desired freq (khz) divisor actual baud rate actual freq (khz) deviation dec hex 50.00 16 x 0.80000 24576 6000 50.00 0.80000 0.0000% 75.00 16 x 1.20000 16384 4000 75.00 1.20000 0.0000% 110.00 16 x 1.76000 11170 2ba2 110.01 1.76014 -0.00081% 300.00 16 x 4.80000 4096 1000 300.00 4.80000 0.0000% 600.00 16 x 9.60000 2048 800 600.00 9.60000 0.0000% 1200.00 16 x 19.20000 1024 400 1200.00 19.20000 0.0000% 2400.00 16 x 38.40000 512 200 2400.00 38.40000 0.0000% 4800.00 16 x 76.80000 256 100 4800.00 76.80000 0.0000% 9600.00 16 x 153.60000 128 80 9600.00 153.60000 0.0000% 19200.00 16 x 307.20000 64 40 19200.00 307.20000 0.0000% 38400.00 16 x 614.40000 32 20 38400.00 614.40000 0.0000% 76800.00 16 x 1228.80000 16 10 76800.00 1228.80000 0.0000% select sci working mode least significant byte initialization most significant byte initialization
197/268 - serial communications interface (sci) serial communications interface (contd) 8.11.6 input signals sin: serial data input . this pin is the serial data input to the sci receiver shift register. 8.11.7 output signals sout: serial data output. this alternate func- tion output signal is the serial data output for the sci transmitter in all operating modes. 8.11.8 interrupts and dma 8.11.8.1 interrupts the sci can generate interrupts as a result of sev- eral conditions. receiver interrupts include data pending, receive errors (overrun, framing and par- ity), as well as address or break pending. trans- mitter interrupts are software selectable for either transmit buffer register empty (bsn set) or for transmit shift register empty (bsn reset) condi- tions. typical usage of the interrupts generated by the sci peripheral are illustrated in figure 90 . the sci peripheral is able to generate interrupt re- quests as a result of a number of events, several of which share the same interrupt vector. it is therefore necessary to poll s_isr, the interrupt status register, in order to determine the active trigger. these bits should be reset by the program- mer during the interrupt service routine. the four major levels of interrupt are encoded in hardware to provide two bits of the interrupt vector register, allowing the position of the block of point- er vectors to be resolved to an 8 byte block size. the sci interrupts have an internal priority struc- ture in order to resolve simultaneous events. refer also to section 8.11.2 for more details relating to synchronous mode. table 42. sci interrupt internal priority receive dma request highest priority transmit dma request receive interrupt transmit interrupt lowest priority
198/268 - serial communications interface (sci) serial communications interface (contd) table 43. sci interrupt vectors figure 90. sci interrupts: example of typical usage interrupt source vector address transmitter buffer or shift register empty transmit dma end of block xxx x110 received data pending receive dma end of block xxxx x100 break detector address word match xxxx x010 receiver error xxxx x000 interrupt break match address data address after break condition address word marked by d9=1 address interrupt interrupt d9=1 d9 acting as data control with separate interrupt character search mode interrupt va00270 break break interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt data interrupt interrupt interrupt data address data data data data no match address break data no match address match data data data match data char match data data data data address data data d9=1 data data data data
199/268 - serial communications interface (sci) serial communications interface (contd) 8.11.8.2 dma two dma channels are associated with the sci, for transmit and for receive. these follow the reg- ister scheme as described in the dma chapter. dma reception to perform a dma transfer in reception mode: 1. initialize the dma counter (rdcpr) and dma address (rdapr) registers 2. enable dma by setting the rxd bit in the idpr register. 3. dma transfer is started when data is received by the sci. dma transmission to perform a dma transfer in transmission mode: 1. initialize the dma counter (tdcpr) and dma address (tdapr) registers. 2. enable dma by setting the txd bit in the idpr register. 3. dma transfer is started by writing a byte in the transmitter buffer register (txbr). if this byte is the first data byte to be transmitted, the dma counter and address registers must be initialized to begin dma transmission at the sec- ond byte. alternatively, dma transfer can be start- ed by writing a dummy byte in the txbr register. dma interrupts when dma is active, the received data pending and the transmitter shift register empty interrupt sources are replaced by the dma end of block re- ceive and transmit interrupt sources. note: to handle dma transfer correctly in trans- mission, the bsn bit in the imr register must be cleared. this selects the transmitter shift register empty event as the dma interrupt source. the transfer of the last byte of a dma data block will be followed by a dma end of block transmit or receive interrupt, setting the txeob or rxeob bit. a typical transmission end of block interrupt rou- tine will perform the following actions: 1. restore the dma counter register (tdcpr). 2. restore the dma address register (tdapr). 3. clear the transmitter shift register empty bit txsem in the s_isr register to avoid spurious interrupts. 4. clear the transmitter end of block (txeob) pending bit in the imr register. 5. set the txd bit in the idpr register to enable dma. 6. load the transmitter buffer register (txbr) with the next byte to transmit. the above procedure handles the case where a further dma transfer is to be performed. error interrupt handling if an error interrupt occurs while dma is enabled in reception mode, dma transfer is stopped. to resume dma transfer, the error interrupt han- dling routine must clear the corresponding error flag. in the case of an overrun error, the routine must also read the rxbr register. character search mode with dma in character search mode with dma, when a character match occurs, this character is not trans- ferred. dma continues with the next received char- acter. to avoid an overrun error occurring, the character match interrupt service routine must read the rxbr register.
200/268 - serial communications interface (sci) serial communications interface (contd) 8.11.9 register description the sci registers are located in the following pag- es in the st9: sci number 0: page 24 (18h) sci number 1: page 25 (19h) (when present) the sci is controlled by the following registers: address register r240 (f0h) receiver dma transaction counter pointer register r241 (f1h) receiver dma source address pointer register r242 (f2h) transmitter dma transaction counter pointer register r243 (f3h) transmitter dma destination address pointer register r244 (f4h) interrupt vector register r245 (f5h) address compare register r246 (f6h) interrupt mask register r247 (f7h) interrupt status register r248 (f8h) receive buffer register same address as transmitter buffer register (read only) r248 (f8h) transmitter buffer register same address as receive buffer register (write only) r249 (f9h) interrupt/dma priority register r250 (fah) character configuration register r251 (fbh) clock configuration register r252 (fch) baud rate generator high register r253 (fdh) baud rate generator low register r254 (feh) reserved r255 (ffh) reserved
201/268 - serial communications interface (sci) serial communications interface (contd) receiver dma counter pointer (rdcpr) r240 - read/write reset value: undefined bit 7:1 = rc[7:1] : receiver dma counter pointer. these bits contain the address of the receiver dma transaction counter in the register file. bit 0 = rr/m : receiver register file/memory se- lector . 0: select memory space as destination. 1: select the register file as destination. receiver dma address pointer (rdapr) r241 - read/write reset value: undefined bit 7:1 = ra[7:1] : receiver dma address pointer. these bits contain the address of the pointer (in the register file) of the receiver dma data source. bit 0 = rps : receiver dma memory pointer se- lector. this bit is only significant if memory has been se- lected for dma transfers (rr/m = 0 in the rdcpr register). 0: select isr register for receiver dma transfers address extension. 1: select dmasr register for receiver dma trans- fers address extension. transmitter dma counter pointer (tdcpr) r242 - read/write reset value: undefined bit 7:1 = tc[7:1] : transmitter dma counter point- er . these bits contain the address of the transmitter dma transaction counter in the register file. bit 0 = tr/m : transmitter register file/memory selector . 0: select memory space as source. 1: select the register file as source. transmitter dma address pointer (tdapr) r243 - read/write reset value: undefined bit 7:1 = ta[7:1] : transmitter dma address point- er. these bits contain the address of the pointer (in the register file) of the transmitter dma data source. bit 0 = tps : transmitter dma memory pointer se- lector. this bit is only significant if memory has been se- lected for dma transfers (tr/m = 0 in the tdcpr register). 0: select isr register for transmitter dma transfers address extension. 1: select dmasr register for transmitter dma transfers address extension. 70 rc7 rc6 rc5 rc4 rc3 rc2 rc1 rr/m 70 ra7 ra6 ra5 ra4 ra3 ra2 ra1 rps 70 tc7 tc6 tc5 tc4 tc3 tc2 tc1 tr/m 70 ta7 ta6 ta5 ta4 ta3 ta2 ta1 tps
202/268 - serial communications interface (sci) serial communications interface (contd) interrupt vector register (s_ivr) r244 - read/write reset value: undefined bit 7:3 = v[7:3] : sci interrupt vector base ad- dress. user programmable interrupt vector bits for trans- mitter and receiver. bit 2:1 = ev[2:1] : encoded interrupt source. both bits ev2 and ev1 are read only and set by hardware according to the interrupt source. bit 0 = d0 : this bit is forced by hardware to 0. address/data compare register (acr) r245 - read/write reset value: undefined bit 7:0 = ac[7:0] : address/compare character . with either 9th bit address mode, address after break mode, or character search, the received ad- dress will be compared to the value stored in this register. when a valid address matches this regis- ter content, the receiver address pending bit (rxap in the s_isr register) is set. after the rxap bit is set in an addressed mode, all received data words will be transferred to the receiver buff- er register. 70 v7 v6 v5 v4 v3 ev2 ev1 0 ev2 ev1 interrupt source 0 0 receiver error (overrun, framing, parity) 0 1 break detect or address match 10 received data pending/receiver dma end of block 11 transmitter buffer or shift register empty transmitter dma end of block 70 ac7ac6ac5ac4ac3ac2ac1ac0
203/268 - serial communications interface (sci) serial communications interface (contd) interrupt mask register (imr) r246 - read/write reset value: 0xx00000 bit 7 = bsn : buffer or shift register empty inter- rupt . this bit selects the source of the transmitter regis- ter empty interrupt. 0: select a shift register empty as source of a transmitter register empty interrupt. 1: select a buffer register empty as source of a transmitter register empty interrupt. bit 6 = rxeob : received end of block. this bit is set by hardware only and must be reset by software. rxeob is set after a receiver dma cycle to mark the end of a data block. 0: clear the interrupt request. 1: mark the end of a received block of data. bit 5 = txeob : transmitter end of block. this bit is set by hardware only and must be reset by software. txeob is set after a transmitter dma cycle to mark the end of a data block. 0: clear the interrupt request. 1: mark the end of a transmitted block of data. bit 4 = rxe : receiver error mask. 0: disable receiver error interrupts (oe, pe, and fe pending bits in the s_isr register). 1: enable receiver error interrupts. bit 3 = rxa : receiver address mask . 0: disable receiver address interrupt (rxap pending bit in the s_isr register). 1: enable receiver address interrupt. bit 2 = rxb : receiver break mask . 0: disable receiver break interrupt (rxbp pend- ing bit in the s_isr register). 1: enable receiver break interrupt. bit 1 = rxdi : receiver data interrupt mask . 0: disable receiver data pending and receiver end of block interrupts (rxdp and rxeob pending bits in the s_isr register). 1: enable receiver data pending and receiver end of block interrupts. note: rxdi has no effect on dma transfers. bit 0 = txdi : transmitter data interrupt mask . 0: disable transmitter buffer register empty, transmitter shift register empty, or transmitter end of block interrupts (txbem, txsem, and txeob bits in the s_isr register). 1: enable transmitter buffer register empty, transmitter shift register empty, or transmitter end of block interrupts. note: txdi has no effect on dma transfers. 70 bsn rxeob txeob rxe rxa rxb rxdi txdi
204/268 - serial communications interface (sci) serial communications interface (contd) interrupt status register (s_isr) r247 - read/write reset value: undefined bit 7 = oe : overrun error pending . this bit is set by hardware if the data in the receiv- er buffer register was not read by the cpu before the next character was transferred into the receiv- er buffer register (the previous data is lost). 0: no overrun error. 1: overrun error occurred. bit 6 = fe : framing error pending bit . this bit is set by hardware if the received data word did not have a valid stop bit. 0: no framing error. 1: framing error occurred. note: in the case where a framing error occurs when the sci is programmed in address mode and is monitoring an address, the interrupt is as- serted and the corrupted data element is trans- ferred to the receiver buffer register. bit 5 = pe : parity error pending . this bit is set by hardware if the received word did not have the correct even or odd parity bit. 0: no parity error. 1: parity error occurred. bit 4 = rxap : receiver address pending . rxap is set by hardware after an interrupt ac- knowledged in the address mode. 0: no interrupt in address mode. 1: interrupt in address mode occurred. note: the source of this interrupt is given by the couple of bits (amen, am) as detailed in the idpr register description. bit 3 = rxbp : receiver break pending bit . this bit is set by hardware if the received data in- put is held low for the full word transmission time (start bit, data bits, parity bit, stop bit). 0: no break received. 1: break event occurred. bit 2 = rxdp : receiver data pending bit. this bit is set by hardware when data is loaded into the receiver buffer register. 0: no data received. 1: data received in receiver buffer register. bit 1 = txbem : transmitter buffer register emp- ty . this bit is set by hardware if the buffer register is empty. 0: no buffer register empty event. 1: buffer register empty. bit 0 = txsem : transmitter shift register empty . this bit is set by hardware if the shift register has completed the transmission of the available data. 0: no shift register empty event. 1: shift register empty. note: the interrupt status register bits can be re- set but cannot be set by the user. the interrupt source must be cleared by resetting the related bit when executing the interrupt service routine (natu- rally the other pending bits should not be reset). 70 oe fe pe rxap rxbp rxdp txbem txsem
205/268 - serial communications interface (sci) serial communications interface (contd) receiver buffer register (rxbr) r248 - read only reset value: undefined bit 7:0 = rd[7:0] : received data. this register stores the data portion of the re- ceived word. the data will be transferred from the receiver shift register into the receiver buffer register at the end of the word. all receiver inter- rupt conditions will be updated at the time of trans- fer. if the selected character format is less than 8 bits, unused most significant bits will forced to 1. note: rxbr and txbr are two physically differ- ent registers located at the same address. transmitter buffer register (txbr) r248 - write only reset value: undefined bit 7:0 = td[7:0] : transmit data . the st9 core will load the data for transmission into this register. the sci will transfer the data from the buffer into the shift register when availa- ble. at the transfer, the transmitter buffer register interrupt is updated. if the selected word format is less than 8 bits, the unused most significant bits are not significant. note: txbr and rxbr are two physically differ- ent registers located at the same address. 70 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 70 td7 td6 td5 td4 td3 td2 td1 td0
206/268 - serial communications interface (sci) serial communications interface (contd) interrupt/dma priority register (idpr) r249 - read/write reset value: undefined bit 7 = amen : address mode enable. this bit, together with the am bit (in the chcr reg- ister), decodes the desired addressing/9th data bit/character match operation. in address mode the sci monitors the input serial data until its address is detected note: upon reception of address, the rxap bit (in the interrupt status register) is set and an inter- rupt cycle can begin. the address character will not be transferred into the receiver buffer regis- ter but all data following the matched sci address and preceding the next address word will be trans- ferred to the receiver buffer register and the proper interrupts updated. if the address does not match, all data following this unmatched address will not be transferred to the receiver buffer reg- ister. in any of the cases the rxap bit must be reset by software before the next word is transferred into the buffer register. when amen is reset and am is set, a useful char- acter search function is performed. this allows the sci to generate an interrupt whenever a specific character is encountered (e.g. carriage return). bit 6 = sb : set break . 0: stop the break transmission after minimum break length. 1: transmit a break following the transmission of all data in the transmitter shift register and the buffer register. note: the break will be a low level on the transmit- ter data output for at least one complete word for- mat. if software does not reset sb before the min- imum break length has finished, the break condi- tion will continue until software resets sb. the sci terminates the break condition with a high level on the transmitter data output for one transmission clock period. bit 5 = sa : set address . if an address/9th data bit mode is selected, sa val- ue will be loaded for transmission into the shift register. this bit is cleared by hardware after its load. 0: indicate it is not an address word. 1: indicate an address word. note: proper procedure would be, when the transmitter buffer register is empty, to load the value of sa and then load the data into the trans- mitter buffer register. bit 4 = rxd : receiver dma mask . this bit is reset by hardware when the transaction counter value decrements to zero. at that time a receiver end of block interrupt can occur. 0: disable receiver dma request (the rxdp bit in the s_isr register can request an interrupt). 1: enable receiver dma request (the rxdp bit in the s_isr register can request a dma transfer). bit 3 = txd : transmitter dma mask . this bit is reset by hardware when the transaction counter value decrements to zero. at that time a transmitter end of block interrupt can occur. 0: disable transmitter dma request (txbem or txsem bits in s_isr can request an interrupt). 1: enable transmitter dma request (txbem or txsem bits in s_isr can request a dma trans- fer). bit 2:0 = prl[2:0] : sci interrupt/dma priority bits . the priority for the sci is encoded with (prl2,prl1,prl0). priority level 0 is the highest, while level 7 represents no priority. when the user has defined a priority level for the sci, priorities within the sci are hardware defined. these sci internal priorities are: 70 amen sb sa rxd txd prl2 prl1 prl0 amen am 0 0 address interrupt if 9th data bit = 1 0 1 address interrupt if character match 10 address interrupt if character match and 9th data bit =1 11 address interrupt if character match with word immediately following break receiver dma request highest priority transmitter dma request receiver interrupt transmitter interrupt lowest priority
207/268 - serial communications interface (sci) serial communications interface (contd) character configuration register (chcr) r250 - read/write reset value: undefined bit 7 = am : address mode . this bit, together with the amen bit (in the idpr register), decodes the desired addressing/9th data bit/character match operation. please refer to the table in the idpr register description. bit 6 = ep : even parity . 0: select odd parity (when parity is enabled). 1: select even parity (when parity is enabled). bit 5 = pen : parity enable . 0: no parity bit. 1: parity bit generated (transmit data) or checked (received data). note: if the address/9th bit is enabled, the parity bit will precede the address/9th bit (the 9th bit is never included in the parity calculation). bit 4 = ab : address/9th bit . 0: no address/9th bit. 1: address/9th bit included in the character format between the parity bit and the first stop bit. this bit can be used to address the sci or as a ninth data bit. bit 3:2 = sb[1:0] : number of stop bits .. bit 1:0 = wl[1:0] : number of data bits clock configuration register (ccr) r251 - read/write reset value: 0000 0000 (00h) bit 7:3 = reserved. must be left at reset value. bit 2 = aen : auto echo enable . 0: no auto echo mode. 1: put the sci in auto echo mode. note: auto echo mode has the following effect: the sci transmitter is disconnected from the data- out pin sout, which is driven directly by the re- ceiver data-in pin, sin. the receiver remains con- nected to sin and is operational, unless loopback mode is also selected. bit 1 = lben : loopback enable . 0: no loopback mode. 1: put the sci in loopback mode. note: in this mode, the transmitter output is set to a high level, the receiver input is disconnected, and the output of the transmitter shift register is looped back into the receiver shift register input. all interrupt sources (transmitter and receiver) are operational. bit 0 = stpen : stick parity enable . 0: the transmitter and the receiver will follow the parity of even parity bit ep in the chcr register. 1: the transmitter and the receiver will use the op- posite parity type selected by the even parity bit ep in the chcr register. 70 am ep pen ab sb1 sb0 wl1 wl0 sb1 sb0 number of stop bits 00 1 0 1 1.5 10 2 1 1 2.5 wl1 wl0 data length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits 70 -----aenlbenstpen ep spen parity (transmitter & receiver) 0 (odd) 0 odd 1 (even) 0 even 0 (odd) 1 even 1 (even) 1 odd
208/268 - serial communications interface (sci) serial communications interface (contd) baud rate generator high register (brghr) r252 - read/write reset value: undefined baud rate generator low register (brglr) r253 - read/write reset value: undefined bit 15:0 = baud rate generator msb and lsb. the baud rate generator is a programmable di- vide by n counter which can be used to generate the clocks for the transmitter and/or receiver. this counter divides the clock input by the value in the baud rate generator register. the minimum baud rate divisor is 2 and the maximum divisor is 2 16 -1. after initialization of the baud rate genera- tor, the divisor value is immediately loaded into the counter. this prevents potentially long random counts on the initial load. if set to 0 or 1, the baud rate generator is stopped. input control (sicr) r254 - read/write reset value: 0000 0011 (03h) bit 7 = reserved. bit 6 = inpl : sin input polarity . 0: polarity not inverted. 1: polarity inverted. note: inpl only affects received data. in auto- echo mode sout = sin even if inpl is set. in loop-back mode the state of the inpl bit is irrele- vant. bit 5:3 = reserved. bit 2 = inpen : input disable . 0: enable sin input 1: disable sin input bit 1:0 = reserved. output control (socr) r255 - read/write reset value: 0000 0001 (01h) bit 7 = outpl : sout output polarity. 0: polarity not inverted. 1: polarity inverted. note: outpl only affects the data sent by the transmitter section. in auto-echo mode sout = sin even if outpl=1. in loop-back mode, the state of outpl is irrelevant. bit 6 = outsb : sout output stand-by level . 0: sout stand-by level is high. 1: sout stand-by level is low. bit 5:0 = reserved. 15 8 bg15 bg14 bg13 bg12 bg11 bg10 bg9 bg8 70 bg7 bg6 bg5 bg4 bg3 bg2 bg1 bg0 70 - inpl - - - inpen - - 70 outploutsb------
209/268 - voltage synthesis tuning converter (vs) 8.12 voltage synthesis tuning converter (vs) 8.12.1 description the on-chip voltage synthesis (vs) converter al- lows the generation of a tuning reference voltage in a tv set application. the peripheral is com- posed of a 14-bit counter that allows the conver- sion of the digital content in a tuning voltage, avail- able at the vs output pin, by using pwm (pulse width modulation) and brm (bit rate modulation) techniques. the 14-bit counter gives 16384 steps which allow a resolution of approximately 2 mv over a tuning voltage of 32 v. this corresponds to a tuning resolution of about 40 khz per step in uhf band (the actual value will depend on the characteristics of the tuner). the tuning word consists of a 14-bit word con- tained in the registers vsdr1 (r254) and vsdr2 (r255) both located in page 59. coarse tuning (pwm) is performed using the sev- en most significant bits. fine tuning (brm) is per- formed using the the seven least significant bits. with all 0s loaded, the output is 0. as the tuning voltage increases from all 0s, the number of puls- es in one period increases to 128 with all pulses being the same width. for values larger than 128, the pwm takes over and the number of pulses in one period remains constant at 128, but the width changes. at the other end of the scale, when al- most all 1s are loaded, the pulses will start to link together and the number of pulses will decrease. when all 1s are loaded, the output will be almost 100% high but will have a low pulse (1/16384 of the high pulse). 8.12.2 output waveforms included inside the vs are the register latches, a reference counter, pwm and brm control circuit- ry. the clock for the 14-bit reference counter is de- rived from the main system clock (referred to as intclk) after a division by 4. for example, using an internal 12 mhz on-chip clock (see timing & clock controller chapter) leads to a 3 mhz input for the vs counter. from the point of view of the circuit, the seven most significant bits control the coarse tuning, while the seven least significant bits control the fine tuning. from the application and software point of view, the 14 bits can be considered as one binary number. as already mentioned the coarse tuning consists of a pwm signal with 128 steps: we can consider the fine tuning to cover 128 coarse tuning cycles. the vs tuning converter is implemented with 2 separate outputs (vso1 and vso2) that can drive 2 separate alternate function outputs of 2 stand- ard i/o port bits. a control bit allows you to choose which output is activated (only one output can be activated at a time). when a vs output is not selected because the vs is disabled or because the second output is select- ed, it stays at a logical one level, allowing you to use the corresponding i/o port bit either as a nor- mal i/o port bit or for a possible second alternate function output. a second control bit allows the vs function to be started (or stopped) by software.
210/268 - voltage synthesis tuning converter (vs) voltage synthesis (contd) pwm generation the counter increments continuously, clocked at intclk divided by 4. whenever the 7 least signif- icant bits of the counter overflow, the vs output is set. the state of the pwm counter is continuously compared to the value programmed in the 7 most significant bits of the tuning word. when a match occurs, the output is reset thus generating the pwm output signal on the vs pin. this pulse width modulated signal must be fil- tered, using an external rc network placed as close as possible to the associated pin. this pro- vides an analog voltage proportional to the aver- age charge passed to the external capacitor. thus for a higher mark/space ratio (high time much greater than low time) the average output voltage is higher. the external components of the rc net- work should be selected for the filtering level re- quired for control of the system variable. figure 91. typical pwm output filter figure 92. pwm generation c ext output voltage r ext pwm out 1k counter 127 7-bit pwm value overflow overflow overflow 000 t pwm output t intclk/4 x 128
211/268 - voltage synthesis tuning converter (vs) voltage synthesis (contd) figure 93. pwm simplified voltage output after filtering (2 examples) v dd 0v 0v dd v v ripple (mv) v outavg "charge" "discharge" "charge" "discharge" 0v v v 0v outavg v (mv) ripple v vr01956 "charge" "discharge" "charge" "discharge" pwmout dd dd pwmout output voltage output voltage
212/268 - voltage synthesis tuning converter (vs) voltage synthesis (contd) brm generation the brm bits allow the addition of a pulse to wid- en a standard pwm pulse for specific pwm cy- cles. this has the effect of fine-tuning the pwm duty cycle (without modifying the base duty cycle), thus, with the external filtering, providing additional fine voltage steps. the incremental pulses (with duration of t intclk / 4) are added to the beginning of the original pwm pulse and thus cause the pwm high time to be ex- tended by this time with a corresponding reduction in the low time. the pwm intervals which are add- ed to are specified in the lower 7 bits of the tuning word and are encoded as shown in the following table. table 44. 7-bit brm pulse addition positions the brm values shown may be combined togeth- er to provide a summation of the incremental pulse intervals specified. the pulse increment corresponds to the pwm res- olution. figure 94. simplified filtered voltage output schematic with brm added fine tuning no. of pulses added at the following cycles 0000001 64 0000010 32, 96 0000100 16, 48, 80, 112 0001000 8, 24,... 104, 120 0010000 4, 12,... 116, 124 0100000 2, 6,... 122, 126 1000000 1, 3,... 125, 127 v dd pwmout 0v v dd output voltage 0v brm = 1 brm = 0 t intclk /4 brm extended pulse == =
213/268 - voltage synthesis tuning converter (vs) voltage synthesis (contd) 8.12.3 register description vs data and control register 1 (vsdr1) r254 - read/write register page: 59 reset value: 0000 0000 (00h) bit 7 = vse : vs enable bit. 0: vs tuning converter disabled (i.e. the clock is not forwarded to the vs counter and the 2 out- puts are set to 1 (idle state) 1: vs tuning converter enabled. bit 6 = vswp : vs output select this bit controls which vs output is enabled to out- put the vs signal. 0: vso1 output selected 1: vso2 output selected bit 5:0 = vd[13:8] tuning word bits. these bits are the 6 most significant bits of the tuning word forming the pwm selection. the vd13 bit is the msb. vs data and control register 2 (vsdr2) r255 - read/write register page: 59 reset value: 0000 0000 (00h) bit 7:0 = vd[7:0] tuning word bits. these bits are the 8 least significant data bits of the vs tuning word. all bits are accessible. bits vd6 - vd0 form the brm pulse selection. vd7 is the lsb of the 7 bits forming the pwm selection. 76543210 vse vswp vd13 vd12 vd11 vd10 vd9 vd8 70 vd7 vd6 vd5 vd4 vd3 vd2 vd1 vd0
214/268 - pwm generator 8.13 pwm generator 8.13.1 introduction the pwm (pulse width modulated) signal genera- tor allows the digital generation of up to 8 analog outputs when used with an external filtering net- work. the unit is based around an 8-bit counter which is driven by a programmable 4-bit prescaler, with an input clock signal equal to the internal clock intclk divided by 2. for example, with a 12 mhz internal clock, using the full 8-bit resolution, a fre- quency range from 1465 hz up to 23437 hz can be achieved. higher frequencies, with lower resolution, can be achieved by using the autoclear register. as an ex- ample, with a 12 mhz internal clock, a maximum pwm repetition rate of 93750 hz can be reached with 6-bit resolution. note: the number of output pins is device de- pendant. refer to the device pinout description. figure 95. pwm block diagram. autoclear compare 7 compare 6 compare 5 compare 4 compare 3 compare 2 compare 1 compare 0 vr01765 pwm7 pwm0 8 bit counter 4 bit presc. control logic intclk/2 output logic st9 register bus
215/268 - pwm generator pwm generator (contd) up to 8 pwm outputs can be selected as alternate functions of an i/o port. each output bit is inde- pendently controlled by a separate compare reg- ister. when the value programmed into the com- pare register and the counter value are equal, the corresponding output bit is set. the output bit is re- set by a counter clear (by overflow or autoclear), generating the variable pwm signal. each output bit can also be complemented or dis- abled under software control. 8.13.2 register mapping the st9 can have one or two pwm generators. each has 13 registers mapped in page 59 (pwm0) or page 58 (pwm1). in the register description on the following pages, the register page refers to pwm0 only. figure 96. pwm action when compare register = 0 (no complement) figure 97. pwm action when compare register = 3 (no complement) register address register function r240 cm0 ch. 0 compare register r241 cm1 ch. 1 compare register r242 cm2 ch. 2 compare register r243 cm3 ch. 3 compare register r244 cm4 ch. 4 compare register r245 cm5 ch. 5 compare register r246 cm6 ch. 6 compare register r247 cm7 ch. 7 compare register r248 acr autoclear register r249 crr counter read register r250 pctlr prescaler/ reload reg. r251 ocplr output complement reg. r252 oer output enable register r253- r255 reserved vr0a1814 pwm clock pwm output counter=autoclear value counter=0 counter=1 vr001814 pwm clock pwm output counter=autoclear value counter=0 counter=3
216/268 - pwm generator pwm generator (contd) 8.13.2.1 register description compare register 0 (cm0) r240 - read/write register page: 59 reset value: 0000 0000 (00h) this is the compare register controlling pwm out- put 0. when the programmed content is equal to the counter content, a set operation is performed on pwm output 0 (if the output has not been com- plemented or disabled). bit 7:0 = cm0.[7:0] : pwm compare value chan- nel 0. compare register 1 (cm1) r241 - read/write register page: 59 reset value: 0000 0000 (00h) this is the compare register controlling pwm out- put 1. compare register 2 (cm2) r242 - read/write register page: 59 reset value: 0000 0000 (00h) this is the compare register controlling pwm out- put 2. compare register 3 (cm3) r243 - read/write register page: 59 reset value: 0000 0000 (00h) this is the compare register controlling pwm out- put 3. compare register 4 (cm4) r244 - read/write register page: 59 reset value: 0000 0000 (00h) this is the compare register controlling pwm out- put 4. compare register 5 (cm5) r245 - read/write register page: 59 reset value: 0000 0000 (00h) this is the compare register controlling pwm out- put 5. compare register 6 (cm6) r246 - read/write register page: 59 reset value: 0000 0000 (00h) this is the compare register controlling pwm out- put 6. compare register 7 (cm7) r247 - read/write register page: 59 reset value: 0000 0000 (00h) this is the compare register controlling pwm out- put 7. 70 cm0.7 cm0.6 cm0.5 cm0.4 cm0.3 cm0.2 cm0.1 cm0.0 70 cm1.7 cm1.6 cm1.5 cm1.4 cm1.3 cm1.2 cm1.1 cm1.0 70 cm2.7 cm2.6 cm2.5 cm2.4 cm2.3 cm2.2 cm2.1 cm2.0 70 cm3.7 cm3.6 cm3.5 cm3.4 cm3.3 cm3.2 cm3.1 cm3.0 70 cm4.7 cm4.6 cm4.5 cm4.4 cm4.3 cm4.2 cm4.1 cm4.0 70 cm5.7 cm5.6 cm5.5 cm5.4 cm5.3 cm5.2 cm5.1 cm5.0 70 cm6.7 cm6.6 cm6.5 cm6.4 cm6.3 cm6.2 cm6.1 cm6.0 70 cm7.7 cm7.6 cm7.5 cm7.4 cm7.3 cm7.2 cm7.1 cm7.0
217/268 - pwm generator pwm generator (contd) autoclear register (acr) r248 - read/write register page: 59 reset value: 1111 1111 (ffh) this register behaves exactly as a 9th compare register, but its effect is to clear the crr counter register, so causing the desired pwm repetition rate. the reset condition generates the free running mode. so, ffh means count by 256. bit 7:0 = ac[7:0] : autoclear count value. when 00 is written to the compare register, if the acr register = ffh, the pwm output bit is always set except for the last clock count (255 set and 1 reset; the converse when the output is comple- mented). if the acr content is less than ffh, the pwm output bit is set for a number of clock counts equal to that content (see figure 2). writing the compare register constant equal to the acr register value causes the output bit to be al- ways reset (or set if complemented). example: if 03h is written to the compare regis- ter, the output bit is reset when the crr counter reaches the acr register value and set when it reaches the compare register value (after 4 clock counts, see figure 97 ). the action will be reversed if the output is complemented. the pwm mark/ space ratio will remain constant until changed by software writing a new value in the acr register. counter register (crr) r249 - read only register page: 59 reset value: 0000 0000 (00h) this read-only register returns the current counter value when read. the 8 bit counter is initialized to 00h at reset, and is a free running up counter. bit 7:0 = cr[7:0] : current counter value. prescaler and control register (pctl) r250 - read/write register page: 59 reset value: 0000 1100 (0ch) bit 7:4 = pr[3:0] pwm prescaler value . these bits hold the prescaler preset value. this is reloaded into the 4-bit prescaler whenever the prescaler (down counter) reaches the value 0, so determining the 8-bit counter count frequency. the value 0 corresponds to the maximum counter frequency which is intclk/2. the value fh corre- sponds to the maximum frequency divided by 16 (intclk/32). the reset condition initializes the prescaler to the maximum counter frequency. bit 3:2 = reserved. forced by hardware to 1 bit 1 = clr : counter clear. this bit when set, allows both to clear the counter, and to reload the prescaler. the effect is also to clear the pwm output. it returns 0 if read. bit 0 = ce : counter enable. this bit enables the counter and the prescaler when set to 1. it stops both when reset without affecting their current value, allowing the count to be suspended and then restarted by software on fly. 70 ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 70 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 70 pr3 pr2 pr1 pr0 1 1 clr ce pr[3:0] divider factor frequency 0 1 intclk/2 (max.) 1 2 intclk/4 2 3 intclk/6 .. .. .. fh 16 intclk/32 (min.)
218/268 - pwm generator pwm generator (contd) output complement register (ocpl) r251- read/write register page 59 reset value: 0000 0000 (00h) this register allows the pwm output level to be complemented on an individual bit basis. in default mode (reset configuration), each com- parison true between a compare register and the counter has the effect of setting the corresponding output. at counter clear (either by autoclear comparison true, software clear or overflow when in free run- ning mode), all the outputs are cleared. by setting each individual bit (ocpl.x) in this reg- ister, the logic value of the corresponding output will be inverted (i.e. reset on comparison true and set on counter clear). example: when set to 1, the ocpl.1 bit comple- ments the pwm output 1. bit 7 = ocpl.7 : complement pwm output 7. bit 6 = ocpl.6 : complement pwm output 6. bit 5 = ocpl.5 : complement pwm output 5. bit 4 = ocpl.4 : complement pwm output 4. bit 3 = ocpl.3 : complement pwm output 3. bit 2 = ocpl.2 : complement pwm output 2. bit 1 = ocpl.1 : complement pwm output 1. bit 0 = ocpl.0 : complement pwm output 0. output enable register (oer) r252 - read/write register page: 59 reset value: 0000 0000 (00h) these bits are set and cleared by software. 0: force the corresponding pwm output to logic level 1. this allows the port pins to be used for normal i/o functions or other alternate functions (if available). 1: enable the corresponding pwm output. example: writing 03h into the oe register will en- able only pwm outputs 0 and 1, while outputs 2, 3, 4, 5, 6 and 7 will be forced to logic level 1. bit 7 = oe.7 : output enable pwm output 7. bit 6 = oe.6 : output enable pwm output 6. bit 5 = oe.5 : output enable pwm output 5. bit 4 = oe.4 : output enable pwm output 4. bit 3 = oe.3 : output enable pwm output 3. bit 2 = oe.2 : output enable pwm output 2. bit 1 = oe.1 : output enable pwm output 1. bit 0 = oe.0 : output enable pwm output 0. 70 ocpl.7 ocpl.6ocpl.5 ocpl.4ocpl.3 ocpl.2 ocpl.1ocpl.0 70 oe.7 oe.6 oe.5 oe.4 oe.3 oe.2 oe.1 oe.0
219/268 - a/d converter (a/d) 8.14 a/d converter (a/d) 8.14.1 introduction the 8 bit analog to digital converter uses a fully differential analog configuration for the best noise immunity and precision performance. the analog voltage references of the converter are connected to the internal av dd & av ss analog supply pins of the chip if they are available, otherwise to the ordi- nary v dd and v ss supply pins of the chip. the guaranteed accuracy depends on the device (see electrical characteristics). a fast sample/hold al- lows quick signal sampling for minimum warping effect and conversion error. 8.14.2 main features n 8-bit resolution a/d converter n single conversion time (including sampling time): C 138 internal system clock periods in slow mode (~5.6 s @25mhz internal system clock); C 78 intclk periods in fast mode (~6.5 s @ 12mhz internal system clock) n sample/hold: tsample= C 84 intclk periods in slow mode (~3.4 s @25mhz internal system clock) C 48 intclk periods in fast mode (~4 s @12mhz internal system clock) n up to 8 analog inputs (the number of inputs is device dependent, see device pinout) n single/continuous conversion mode n external source trigger (alternate synchronization) n power down mode (zero power consumption) n 1 control logic register n 1 data register 8.14.3 general description depending on the device, up to 8 analog inputs can be selected by software. different conversion modes are provided: single, continuous, or triggered. the continuous mode performs a continuous conversion flow of the se- lected channel, while in the single mode the se- lected channel is converted once and then the log- ic waits for a new hardware or software restart. a data register (addtr) is available, mapped in page 62, allowing data storage (in single or contin- uous mode). the start conversion event can be managed either C by software, writing the start/stop bit of the control logic register C or by hardware using an external signal on the extrg triggered input (negative edge sensitive) connected as an alternate function to an i/o port bit figure 98. a/d converter block diagram n st9 bus successive approximation register analog mux data register control logic s/h ain1 ainx ain0 extrg
220/268 - a/d converter (a/d) a/d converter ( contd ) the conversion technique used is successive ap- proximation, with ac coupled analog fully differen- tial comparators blocks plus a sample and hold logic and a reference generator. the internal reference (dac) is based on the use of a binary-ratioed capacitor array. this technique allows the specified monotonicity (using the same ratioed capacitors as sampling capacitor). a pow- er down programmable bit sets the a/d converter analog section to a zero consumption idle status. 8.14.3.1 operating modes the two main operating modes, single and contin- uous, can be selected by writing 0 (reset value) or 1 into the cont bit of the control logic register. single mode in single mode (cont=0 in adclr) the str bit is forced to '0' after the end of channel i-th conver- sion; then the a/d waits for a new start event. this mode is useful when a set of signals must be sam- pled at a fixed frequency imposed by a timer unit or an external generator (through the alternate synchronization feature). a simple software rou- tine monitoring the str bit can be used to save the current value before a new conversion ends (so to create a signal samples table within the in- ternal memory or the register file). furthermore, if the r242.0 bit (register ad-int, bit 0) is set, at the end of conversion a negative edge on the con- nected external interrupt channel (see interrupts chapter) is generated to allow the reading of the converted data by means of an interrupt routine. continuous mode in continuous mode (cont=1 in adclr) a con- tinuous conversion flow is entered by a start event on the selected channel until the str bit is reset by software. at the end of each conversion, the data register (adcdr) content is updated with the last conver- sion result, while the former value is lost. when the conversion flow is stopped, an interrupt request is generated with the same modality previously de- scribed. 8.14.3.2 alternate synchronization this feature is available in both single/continuous modes. the negative edge of external extrg sig- nal can be used to synchronize the conversion start with a trigger pulse. this event can be ena- bled or masked by programming the trg bit in the adclr register. the effect of alternate synchronization is to set the str bit, which is cleared by hardware at the end of each conversion in single mode. in continuous mode any trigger pulse following the first one will be ignored. the synchronization source must pro- vide a pulse (1.5 internal system clock, 125ns @ 12 mhz internal clock) of minimum width, and a period greater (in single mode) than the conver- sion time (~6.5us @ 12 mhz internal clock). if a trigger occurs when the str bit is still '1' (conver- sions still in progress), it is ignored (see electrical characteristics). warning: if the extrg signal is already active when trg bit is set, the conversion starts immedi- ately. 8.14.3.3 power-up operations before enabling any a/d operation mode, set the pow bit of the adclr register at least 60 s be- fore the first conversion starts to enable the bias- ing circuits inside the analog section of the con- verter. clearing the pow bit is useful when the a/d is not used so reducing the total chip power consumption. this state is also the reset configu- ration and it is forced by hardware when the core is in halt state (after a halt instruction execution). 8.14.3.4 register mapping it is possible to have two independent a/d convert- ers in the same device. in this case they are named a/d 0 and a/d 1. if the device has one a/d converter it uses the register addresses of a/d 0. the register map is the following: if two a/d converters are present, the registers are renamed, adding the suffix 0 to the a/d 0 registers and 1 to the a/d 1 registers. register address adn page 62 (3eh) f0h a/d 0 addtr0 f1h a/d 0 adclr0 f2h a/d 0 adint0 f3-f7h a/d 0 reserved f8h a/d 1 addtr1 f9h a/d 1 adclr1 fah a/d 1 adint1 fb-ffh a/d 1 reserved
221/268 - a/d converter (a/d) a/d converter ( contd ) 8.14.4 register description a/d control logic register (adclr) r241 - read/write register page: 62 reset value: 0000 0000 (00h) this 8-bit register manages the a/d logic opera- tions. any write operation to it will cause the cur- rent conversion to be aborted and the logic to be re-initialized to the starting configuration. bit 7:5 = c[2:0] : channel address. these bits are set and cleared by software. they select channel i conversion as follows: bit 4 = fs : fast/slow . this bit is set and cleared by software. 0: fast mode. single conversion time: 78 x intclk (5.75s at intclk = 12 mhz) 1: slow mode. single conversion time: 138 x intclk (11.5s at intclk = 12 mhz) note : fast conversion mode is only allowed for in- ternal speeds which do not exceed 12 mhz. bit 3 = trg : external trigger enable . this bit is set and cleared by software. 0: external trigger disabled. 1: a negative (falling) edge on the extrg pin writes a 1 into the str bit, enabling start of conversion. note: triggering by on chip event is available on devices with the multifunction timer (mft) periph- eral. bit 2 = pow : power enable . this bit is set and cleared by software. 0: disables all power consuming logic. 1: enables the a/d logic and analog circuitry. bit 1 = cont : continuous/single mode select . this bit it set and cleared by software. 0: single mode: after the current conversion ends, the str bit is reset by hardware and the con- verter logic is put in a wait status. to start anoth- er conversion, the str bit has to be set by soft- ware or hardware. 1: select continuous mode, a continuous flow of a/d conversions on the selected channel, start- ing when the str bit is set. bit 0 = str : start/stop . this bit is set and cleared by software. it is also set by hardware when the a/d is synchronized with an external trigger. 0: stop conversion on channel i. an interrupt is generated if the str was previously set and the ad-int bit is set. 1: start conversion on channel i warning: when accessing this register, it is rec- ommended to keep the related a/d interrupt chan- nel masked or disabled to avoid spurious interrupt requests. a/d channel i data register (addtr) r240 - read/write register page: 62 reset value: undefined the result of the conversion of the selected chan- nel is stored in the 8-bit addtr, which is reloaded with a new value every time a conversion ends. 70 c2 c1 c0 fs trg pow cont str c2 c1 c0 channel enabled 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 70 r.7 r.6 r.5 r.4 r.3 r.2 r.1 r.0
222/268 - a/d converter (a/d) a/d converter ( contd ) a/d interrupt register (adint) register page: 62 r242 - read/write reset value: 0000 0001 (01h) bit 7:1 = reserved. bit 0 = ad-int : ad converter interrupt enable . this bit is set and cleared by software. it allows the interrupt source to be switched between the a/d converter and an external interrupt pin (see inter- rupts chapter). 0: a/d interrupt disabled. external pin selected as interrupt source. 1: a/d interrupt enabled 70 - - - - - - - ad-int
223/268 electrical characteristics 9 electrical characteristics the st92196a device contains circuitry to protect the inputs against damage due to high static volt- age or electric field. nevertheless it is advised to take normal precautions and to avoid applying to this high impedance voltage circuit any voltage higher than the maximum rated voltages. it is rec- ommended for proper operation that v in and v out be constrained to the range. v ss ( v in or v out ) v dd to enhance reliability of operation, it is recom- mended to connect unused inputs to an appropri- ate logic voltage level such as v ss or v dd . all the voltages in the following table, are refer- enced to v ss . absolute maximum ratings * current is limited to |<200 m a| into the pin note : stresses above those listed as absolute maximum ratings may cause permanent damage to the device. this is a stress rating o nly and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended p eriods may affect device reliability. recommended operating conditions note 1. 1mhz when a/d is used note 2. for good slicing results, it is advised to set vdda >= 5.3v. remember also that vdda < vdd + 0.3v. symbol parameter value unit v dd 1,2 supply voltage v ss C 0.3 to v ss + 7.0 v v dda analog supply voltage v ss C 0.3 to v dd +0.3 v v i input voltage v ss C 0.3 to v dd +0.3 v v i input voltage v ss C 0.7 to v dd +0.7 * v v o output voltage v ss C 0.3 to v dd +0.3 v v o output voltage v ss C 0.7 to v dd +0.7 * v t stg storage temperature C 55 to + 150 c i inj pin injection current digital and analog input -5 to +5 ma maximum accumulated pin injection current in the device -50 to +50 ma symbol parameter value unit min. max. t a operating temperature -10 75 c v dd operating supply voltage 4.5 5.5 v v dda analog supply voltage 4.5 5.5 v f osce external oscillator frequency 4.0 mhz f intclk internal clock frequency 0 1 24 mhz
224/268 electrical characteristics dc electrical characteristics (v dd = 5v 10% t a = -10c + 75c, unless otherwise specified) note: all i/o ports are configured in bidirectional weak pull-up mode with no dc load external clock pin (oscin) is driven by square wave external clock. no peripheral working. symbol parameter test conditions value unit min. max. v ih input high level ttl 2.0 v cmos 0.7 v dd v v il input low level ttl 0.8 v cmos 0.3 v dd v v ihrs reset input high level 0.8 v dd v v ilrs reset input low level 0.3 v dd v v hyrs reset input hysteresis 0.5 v v ih p2.0 input high level 0.8 v dd v v il p2.0 input low level 0.3 v dd v v ihy p2.0 input hysteresis 0.5 v v ihiic sda4,1/scl4,1 input high level 0.8 v dd v v iliic sda4,1/scl4,1 input low level 0.3 v dd v v ihyiic sda4,1/scl4,1 hysteresis 0.5 v v ihvh hsync/vsync input high level 0.8 v dd v v ilvh hsync/vsync input low level 0.3 v dd v v hyhv hsync/vsync input hysteresis 1.2 v v ihdt syndet1,0 input high level 0.8 v dd v v ildt syndet1,0 input low level 0.3 v dd v v hydt syndet1,0 input hysteresis 0.5 v v oh output high level push pull, iload = C 0.8ma v dd C 0.8 v v ol output low level push pull or open drain, iload = 1.6ma 0.4 v v pp eprom programming voltage 12.8 v i lkio i/o pin input leakage current hi-z input, 0v < v in < v dd 1.0 m a i lkrs reset pin input leakage current 0v < v in < v dd 1.0 m a i lka/d a/d pin input leakage current alternate function open drain 1.0 m a i lkos oscin pin input leakage current 0v < v in < v dd 1.0 m a
225/268 electrical characteristics ac electrical characteristics pin capacitance (v dd = 5v 10%; t a = -10c + 75c, unless otherwise specified) current consumption (v dd = 5v 10%; t a = -10c + 75c, unless otherwise specified) notes : 1. all ports are configured in push-pull output mode (output is high). vsync and hsync are tied to v ss , ccvideo is floating. the internal clock prescaler is in divide-by-1 mode. the external clock pin (oscin) is driven by a square wave external clock at 4 mhz. 2. the cpu is fed by a frequency issued by the on-chip frequency multiplier. the skew corrector frequency multiplier provides a 28 mhz clock. all peripherals are working. 3. all ports are configured in push-pull output mode (output is high). vsync and hsync are tied to v ss , ccvideo is floating. external clock pin (oscin) and reset pins are held low. all peripherals are disabled. 4. all ports are configured in push-pull output mode (output is high). vsync and hsync are tied to v ss , ccvideo is floating. all peripherals are disabled. 5. the cpu is fed by a frequency issued by the on-chip frequency multiplier. the skew corrector frequency multiplier provides a 14mhz clock. osd, a/d, pwm, sync error detector, std timer and wdg timer peripherals are running. symbol parameter conditions value unit typ. max c io pin capacitance digital input/output 810pf symbol parameter conditions value unit typ. max i cc1 run mode current (notes 1, 2) intclk=16mhz 80 100 ma i cc2 run mode current (notes 1, 2) intclk=24mhz 100 120 ma i cc3 run mode current (notes 1, 2) intclk=4mhz 25 30 ma i cc4 run mode current (notes 1, 5) intclk=16mhz 65 78 ma i cca1 analog current (v dda pin) freq. multipliers , a/d, osd, all dacs & slicers on. 45 55 ma i cca2 analog current (v dda pin) freq. multipliers , a/d, osd, dacs & slicers off. 110 a i cca3 analog current (v dda pin) freq. multipliers , a/d, osd, two dacs & one slicer on. 25 30 ma i ilpr reset mode current (note 3) 10 100 m a i halt halt mode current (note 4) 10 100 m a
226/268 electrical characteristics ac electrical characteristics (contd) clock timing (v dd = 5v 10% t a = -10c + 75c, unless otherwise specified) external interrupt timing (rising or falling edge mode; v dd = 5v 10%; t a = -10c + 75c, unless otherwise specified) note: the value in the left hand two columns shows the formula used to calculate the minimum or maximum timing from the oscilla tor clock period, prescale value and number of wait cycles inserted. the value in the rignt hand two columns shows the minimum and maximu m for an external clock at 24 mhz divided by 2, prescale value of zero and zero wait status. external interrupt timing symbol parameter conditions value unit min max tpc oscin clock period intern. div. by 2 41.7 ns intern. div. by 1 83.3 ns trc oscin rise time 12 ns tfc oscin fall time 12 ns twcl oscin low width intern. div. by 2 17 ns intern. div. by 1 38 ns twch oscin high width intern. div. by 2 17 ns intern. div. by 1 38 ns n symbol parameter conditions unit oscin divided by 2 min. oscin not divided by 2 min. min max 1 twlr low level minimum pulse width in rising edge mode 2tpc + 12 tpc + 12 95 ns 2 twhr high level minimum pulse width in rising edge mode 2tpc + 12 tpc + 12 95 ns 3 twlf low level minimum pulse width in falling edge mode 2tpc + 12 tpc + 12 95 ns 4 twhf high level minimum pulse width in falling edge mode 2tpc + 12 tpc + 12 95 ns intn 1 23 4 rising edge detection falling edge detection n = 0-7 va00112
227/268 electrical characteristics ac electrical characteristics (contd) spi timing (v dd = 5v 10% ; t a = -10c + 75c, unless otherwise specified) spi timing skew corrector timing table (v dd = 5v 10%; t a = -10c + 75c, unless otherwise specified) the osd jitter is measured from leading edge to leading edge of a single character row on consecutive tv lines. the value is an envelope of 100 fields *max. value at all cpu operating frequencies n symbol parameter conditions value unit min max 1 tsdi input data set-up time 100 2 thdi input data hold time 1/2 tpc + 100 3 tdov sck to output data valid 100 4 thdo output data hold time -20 5 twskl sck low pulse width 300 6 twskh sck high pulse width 300 sck sdo 5 6 sdi 1 2 4 3 va00109 symbol parameter conditions value max unit tjskw jitter on rgb output 28 mhz skew corrector clock frequency <12 * ns
228/268 electrical characteristics ac electrical characteristics (contd) osd dac characteristics (v dd = 5v 10%; t a = -10c + 75c, unless otherwise specified) (*) output voltage matching of the r,g and b levels on a single device for each of the 8 levels (**) phase matching (50% point on both rise & fall time) on r, g, b, fb lines (fb in dac mode) (***) phase matching (50% point on both rise & fall time) on r, g, b, fb lines (fb in digital mode) (****) 95% of the signal amplitude is reached within the specified clock period symbol parameter conditions value unit min typ max output impedance fb,r,g,b 100 ohm output voltage fb,r,g,b cload = 20 pf rl=100k code = 111 code = 110 code = 101 code = 100 code = 011 code = 010 code = 001 code = 000 0.976 0.863 0.751 0.638 0.525 0.412 0.300 0.157 1.170 1.034 0.899 0.763 0.627 0.491 0.356 0.220 1.364 1.205 1.046 0.887 0.729 0.570 0.411 0.252 v fb = 1 fb = 0 5.0 0.2 v relative voltage accuracy (*) +/-5 % r/g/b to fb 50% point matching fb dac mode (**) 5ns r/g/b to fb 50% point matching fb digital mode (***) 5ns pixel frequency cload = 20 pf 20**** mhz. cload = 10 pf 40**** mhz.
229/268 electrical characteristics ac electrical characteristics (contd) n/a = not applicable cb = capacitance of one bus in pf i 2 c interface electrical specifications symbol parameter standard mode i2c fast mode i2c unit min max min max v il low level input voltage: fixed input levels v dd -related input levels -0.5 -0.5 1.5 0.3 v dd -0.5 -0.5 1.5 0.3 v dd v v ih high level input voltage: v dd -related input levels 0.8 v dd v dd +0.5 0.8 v dd v dd +0.5 v v hys hysteresis of schmitt trigger inputs fixed input levels v dd -related input levels n/a n/a n/a n/a 0.2 0,05 v dd v t sp pulse width of spikes which must be sup- pressed by the input filter n/a n/a 0 ns 50 ns ns v ol1 v ol2 low level output voltage (open drain and open collector) at 3 ma sink current at 6 ma sink current 0 n/a 0.4 n/a 0 0 0.4 0.6 v t of output fall time from vih min to vil max with a bus capacitance from 10 pf to 400 pf with up to 3 ma sink current at v ol1 with up to 6 ma sink current at v ol2 n/a 250 n/a 20+0.1c b 20+0.1c b 250 250 ns i input current each i/o pin with an input voltage between 0.4v and 0.9 v dd max - 10 10 -10 10 m a c capacitance for each i/o pin 10 10 pf
230/268 electrical characteristics ac electrical characteristics (contd) 1)the device must internally provide a hold time of at least 300 ns for the sda signal in order to bridge the unde- fined region of the falling edge of scl 2)the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal cb = total capacitance of one bus line in pf table 45. characteristics of analog input section (v dd = 5v, ta = -10c to 75c) measurement conditions: (*) same dc level on both comparator inputs ac level 40mv for applicated measurement sig- nal (**) corresponds to 25 ire tap voltage i 2 c bus timings symbol parameter standard i 2 c fast i 2 c unit min max min max t buf bus free time between a stop and start con- dition 4.7 1.3 m s t hd:sta hold time start condition. after this period, the first clock pulse is generated 4.0 0.6 m s t low low period of the scl clock 4.7 1.3 m s t high high period of the scl clock 4.0 0.6 m s t su:sta set-up time for a repeated start condition 4.7 0.6 m s t hd:dat data hold time 0 (1) 0 (1) 0.9(2) ns t su:dat data set-up time 250 100 ns t r rise time of both sda and scl signals 1000 20+0.1cb 300 ns tf fall time of both sda and scl signals 300 20+0.1cb 300 ns t su : sto set-up time for stop condition 4.0 0.6 ns cb capacitive load for each bus line 400 400 pf parameter value unit min. typ. max. voltage comparator reference voltage: unit#1 - video black level clamp 1.90 2.00 2.10 v unit#2 - data slicer (**) 2.25 2.35 2.45 v unit#3 - sync slicer 1.70 1.80 1.90 v voltage comparator delay (all units) (*) 150 200 250 ns video clamp: sink current (ccvideo pin at 2.1v dc) 21 42 80 a source current (ccvideo pin at 1.9v dc) 150 300 600 a sink to source current ratio 0.1 0.14 0.18
231/268 electrical characteristics ac electrical characteristics (contd) a/d converter, external trigger timing table ( v dd = 5v +/-10%; t a = -10c to 75c, unless otherwise specified) a/d converter, external trigger timing table a/d converter. analog parameters table ( v dd = 5v +/-10% ; t a = -10c to 75c, unless otherwise specified)) notes: (*) the values are expected at 25 celsius degrees with v dd = 5v (**)'lsbs' , as used here, as a value of v dd /256 (1) @ 24 mhz external clock (2) including sample time (3) it must be considered as the on-chip series resistance before the sampling capacitor (4) dnl error= max {[v(i) -v(i-1)] / lsb-1}inl error= max {[v(i) -v(0)] / lsb-i} absolute accuracy= overall max conversion error n symbol parameter conditions value unit min max 1t low pulse width 1.5 intclk 2t high pulse distance 1.5 intclk 3t ext period/fast mode 78+1 intclk 4t str start conversion delay 0.5 1.5 intclk parameter value unit note typ (*) min max (**) analog input range v ss v dd v conversion time 138 intclk (1,2) sample time 87.51 intclk (1) power-up time 60 s resolution 8 bits differential non linearity 0.5 0.3 1.5 lsbs (4) integral non linearity 2 lsbs (4) absolute accuracy 2 lsbs (4) input resistance 1.5 kohm (3) hold capacitance 1.92 pf extrg 1 2 st (start conversion bit) 3 4 4 vr001401
232/268 electrical characteristics ac electrical characteristics (contd) latch-up and esd ppm requirements parameter conditions value unit esd sensitivity for 10m a4 kv for 1m a2 latch-up performance stmicroelectronics specification for class a no latch-up parameter conditions value unit ppm requirements 100 ppm
233/268 package description 10 package description figure 99. 56-pin shrink plastic dual in line package, 600-mil width figure 100. 64-pin thin quad flat package dim. mm inches min typ max min typ max a 6.35 0.250 a1 0.38 0.015 a2 3.18 4.95 0.125 0.195 b 0.41 0.016 b2 0.89 0.035 c 0.20 0.38 0.008 0.015 d 50.29 53.21 1.980 2.095 e 15.01 0.591 e1 12.32 14.73 0.485 0.580 e 1.78 0.070 ea 15.24 0.600 eb 17.78 0.700 l 2.92 5.08 0.115 0.200 number of pins n56 pdip56s dim mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 d 16.00 0.630 d1 14.00 0.551 d3 12.00 0.472 e 16.00 0.630 e1 14.00 0.551 e3 12.00 0.472 e 0.80 0.031 k 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 64 nd 16 ne 16 l1 l k 0.10mm .004 seating plane
234/268 ordering information 11 ordering information figure 101. sales type coding rules device rom (kbytes) ram (kbytes) data slicers sci mft st92196a7 96 3211 st92196a6 2 211 st92196a4 64 2-1 st92196a3 1 - - st92196a2 48 1 1-- st92196a1 32 1 - - st 92196 a 4 b 4 / xxx family (92196) version rom/ram size package temperature range rom code (three letters) 4 =-10 to +75c b=plastic dip 7=96k rom, 3k ram t=plastic tqfp 6=96k rom, 2k ram 4=64k rom, 2k ram 2=48k rom, 1k ram 1=32k rom/eprom, 1k ram
235/268 ordering information st92196 option list customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no: . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference/rom code* : . . . . . . . . . . . . . . . . . . *the rom code name is assigned by stmicroelectronics. please confirm characteristics of device: device: [ ] st92196a1 [ ] st92196a2 [ ] st92196a3 [ ] st92196a4 [ ] st92196a6 [ ] st92196a7 package: [ ] psdip56 [ ] tqfp64 temperature range: -10c to 75 c osd code: [ ] osd filename _ _ _ _ _ _ _ _ _.osd special marking: [ ] no [ ] yes "_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _" for marking, one line is possible with maximum 14 characters. authorized characters are letters, digits, '.', '-', '/' and spaces only. quantity forecast: [ _ _ _ _ _ _ _] k units per year for a period of [ _ _ ] years. preferred production start date: [ _ _ _ _ _ _ _] (yyyy/mm/dd) customer signature . . . . . . . . . . . . . . . . . . . . . date . . . . . . . . . . . . . . . . . . . . . . . . . . . .
february 2003 236/268 . rev. 3.1 st92e196a/b & st92t196a/b 8/16-bit mcu for tv applications with 128 k eprom/otp, on-screen-display and 1 or 2 data slicers datasheet n register file based 8/16 bit core architecture with run, wfi, and halt modes n -10 to 75c operating temperature range n 24 mhz operation @5v 10% n min. instruction cycle time: 165 ns at 24 mhz n 128 kbytes eprom/otp, 3 or 4 kbytes static ram n 256 bytes of register file n 384 bytes of display ram (osdram) n 56-pin shrink dip packages n 37 fully programmable i/o pins n flexible clock controller for osd, data slicer and core clocks, running from one single low frequency external crystal n enhanced display controller with rows of up to 63 characters per row C 50/60hz and 100/120 hz operation C 525/625 lines operation, 4:3 or 16:9 format C interlaced and progressive scanning C 18x26 or 9x13 character matrix C 384 (18x26) characters, or 1536 (9x13) char- acters definable in rom by user C 512 possible colors, in 4x16-entry palettes C 2 x 16-entry palettes for foreground, and 2 x 16-entry palettes for background C 8 levels of translucency on fast blanking C serial, parallel and extended parallel at- tribute modes C mouse pointers user-definable in rom C 7 character sizes in 18x26 mode, 4 in 9x13 C rounding, fringe, scrolling, flashing, shad- owing, italics, semi-transparent n i 2 c multi-master / slave with 4 channels n serial communications interface (sci) n serial peripheral interface (spi) n 8-channel a/d converter with 6-bit accuracy n 16-bit watchdog timer with 8-bit prescaler n 14-bit voltage synthesis for tuning reference voltage with 2 outputs for 2 tuners n 16-bit standard timer with 8-bit prescaler n 16-bit multi-function timer n eight 8-bit programmable pwm outputs n nmi and 6 external interrupts n 2 data slicers for closed captioning and extended data service data extraction, on 2 independent video sources. support for fcc v-chip and gemstar bitstream decoding n infra-red signal digital pre-processor n 2-channel sync error detection with integrated sync extractor n rich instruction set and 14 addressing modes n versatile development tools, including c- compiler, assembler, linker, source level debugger, emulator and real-time operating systems from third-parties n windows based osd font and screen editor device summary device memory ram prog. osd font st92e196a9 128k eprom 4k no st92t196a9 128k otp st92e196b7 128k eprom 3k yes st92t196b7 128k otp psdip56 csdip56w
237/268 st92e196a/b & st92t196a/b general description 1general description 1.1 introduction the st92e196a/b and st92t196a/b microcon- trollers are the eprom/otp versions of the st92196a rom devices and are suitable for prod- uct prototyping and low volume production. their performance derives from the use of a flexible 256-register programming model for ultra-fast con- text switching and real-time event response. the intelligent on-chip peripherals offload the st9 core from i/o and data management processing tasks allowing critical application tasks to get the maxi- mum use of core resources. the st92e196a/b and st92t196a/b devices support low power consumption and low voltage operation for power- efficient and low-cost embedded systems. 1.1.1 core architecture the nucleus of the st92196a/b is the enhanced st9 core that includes the central processing unit (cpu), the register file, the interrupt and dma controller. three independent buses are controlled by the core: a 16-bit memory bus, an 8-bit register ad- dressing bus and a 6-bit interrupt/dma bus which connects the interrupt and dma controllers in the on-chip peripherals with the core. this multiple bus architecture makes the st9 fam- ily devices highly efficient for accessing on and off-chip memory and fast exchange of data with the on-chip peripherals. the general-purpose registers can be used as ac- cumulators, index registers, or address pointers. adjacent register pairs make up 16-bit registers for addressing or 16-bit processing. although the st9 has an 8-bit alu, the chip handles 16-bit opera- tions, including arithmetic, loads/stores, and mem- ory/register and memory/memory exchanges. many opcodes specify byte or word operations, the hardware automatically handles 16-bit opera- tions and accesses. for interrupts or subroutine calls, the cpu uses a system stack in conjunction with the stack pointer (sp). a separate user stack has its own sp. the separate stacks, without size limitations, can be in on-chip ram (or in register file) or off-chip mem- ory. 1.1.2 instruction set the st9 instruction set consists of 94 instruction types, including instructions for bit handling, byte (8-bit) and word (16-bit) data, as well as bcd and boolean formats. instructions have been added to facilitate large program and data handling through the mmu, as well as to improve the performance and code density of c function calls. 14 address- ing modes are available, including powerful indi- rect addressing capabilities. the st9's bit-manipulation instructions are set, clear, complement, test and set, load, and various logic instructions (and, or, and xor). math func- tions include add, subtract, increment, decrement, decimal adjust, multiply, and divide. 1.1.3 operating modes to optimize performance versus the power con- sumption of the device, st9 devices now support a range of operating modes that can be dynami- cally selected depending on the performance and functionality requirements of the application at a given moment. run mode. this is the full speed execution mode with cpu and peripherals running at the maximum clock speed delivered by the phase locked loop (pll) of the clock control unit (ccu). slow mode . power consumption can be signifi- cantly reduced by running the cpu and the periph- erals at reduced clock speed using the cpu pres- caler and ccu clock divider. wait for interrupt mode. the wait for interrupt (wfi) instruction suspends program execution un- til an interrupt request is acknowledged. during wfi, the cpu clock is halted while the peripheral and interrupt controller keep running at a frequen- cy programmable via the ccu. in this mode, the power consumption of the device can be reduced by more than 95% (low power wfi). halt mode. when executing the halt instruction, and if the watchdog is not enabled, the cpu and its peripherals stop operating and the status of the machine remains frozen (the clock is also stopped). a reset is necessary to exit from halt mode.
238/268 st92e196a/b & st92t196a/b general description introduction (contd) figure 102. st92e196a/b & st92t196a/b architectural block diagram watchdog timer 256 bytes register file 3k or 4k ram st9+ core 8/16 bits cpu dma/interrupt management memory bus rccu cc data slicer 1 register bus a/d converter ccvideo1 dsout1 sci* 128k eprom/otp ain[7:0] extrg sin0 sout0 all alternate functions ( italic characters ) are mapped on ports 0, 2, 3, 4, and 5 sda[4:0] scl[4:0] mf timer oscin oscout reset reseti 4 ch. i 2 c bus p0[7:0] p2[7:0] p3[7:0] p4[7:0] p5[6:5,2:0] tina tinb touta toutb int[7:0] nmi fully prog. i/os sdio sck spi osdram controller 384 bytes ram infra-red preprocessor pwm dac cc data slicer 2 sync error detector osd voltage synthesis ir pwm[7:0] syndet0 syndet1 vso1 vso2 ccvideo2 dsout2 hsync vsync r/g/b/fb tslu pixclk frequency multiplier fcpu fosd stim timer
239/268 st92e196a/b & st92t196a/b general description introduction (contd) 1.1.4 on-chip peripherals osd controller the on screen display displays closed caption or extended service format data received from the on-chip data slicers or any text or menu data gen- erated by the application. rows of up to 63 charac- ters can be displayed with two user-definable fonts. colors, character shape and other attributes are software programmable. support is provided for mouse or other pointing devices. parallel i/o ports the st9 is provided with dedicated lines for input/ output. these lines, grouped into 8-bit ports, can be independently programmed to provide parallel input/output or to carry input/output signals to or from the on-chip peripherals and core e.g. sci and multifunction timer. all ports have active pull-ups and pull-down resistors compatible with ttl loads. in addition pull-ups can be turned off for open drain operation and weak pull-ups can be turned on to save chip resistive pull-ups. input buffers can be either ttl or cmos compatible. multifunction timer the multifunction timer has a 16-bit up/down counter supported by two 16-bit compare regis- ters and two 16-bit input capture registers. timing resolution can be programmed using an 8-bit pres- caler. serial communications controller the sci provides an asynchronous serial i/o port using two dma channels. baud rates and data for- mats are programmable. controller applications can further benefit from the self test and address wake-up facility offered by the character search mode. i 2 c bus interface the i 2 c bus is a synchronous serial bus for con- necting multiple devices using a data line and a clock line. multimaster and slave modes are sup- ported. up to four channels are supported. the i 2 c interface supports 7-bit addressing. it operates in multimaster or slave mode and supports speeds of up to 666.67 khz. bus events (bus busy, slave ad- dress recognised) and error conditions are auto- matically flagged in peripheral registers and inter- rupts are optionally generated. analog/digital converter the adc provides up to 8 analog inputs with on- chip sample and hold. conversion can be trig- gered by a signal from the mft.
240/268 st92e196a/b & st92t196a/b general description 1.2 pin description figure 103. 56-pin package pin-out table 46. power supply pins table 47. primary function pins 156 29 28 v pp test0 p5.2/sout0 p5.1/sin0 p5.0/reseti reset p4.7/pwm7/extrg p4.6/pwm6 p4.5/pwm5 p4.4/pwm4 p4.3 p4.2 p4.1/sda4/tinb/pwm1 p4.0/scl4/toutb/pwm0 oscin v ss2 oscout p2.3/ain3/vso2/int4 p2.2/ain2/vso1/int3 p2.1/ain1/int6 p2.0/ir/int7 hsync vsync fosd v dda fcpu v ss1 v dd1 pwm2/p5.5 pwm3/p5.6 sck/scl1/int2/p2.4 sdio/sda1p2.5 nmi/p2.6 pixclk/int5/p2.7 ain7/p0.7 ain6/p0.6 ain5/p0.5 ain4/p0.4 ain0/p0.3 p0.2 p0.1 p0.0 ccvideo1 v dd2 ccvideo2/p3.7 dsout1/syndet0/p3.6 tina/sda2/p3.5 int1/touta/scl2/p3.4 dsout2/syndet1/p3.3 int0/p3.2 sda3/p3.1 tslu/scl3/p3.0 fb b g r name function sdip56 v dd1 v dd2 main power supply voltage (2 pins internally connected) 29 16 v ss1 v ss2 analog and digital circuit ground (2 pins internally connected) 30 41 v dda analog circuit supply voltage 32 v pp eprom programming voltage. must be connected to v dd in normal operat- ing mode. 56 name function sdip56 oscin oscillator input 42 oscout oscillator output 40 reset reset to initialize the st9 51 hsync video horizontal sync input (schmitt trigger) 35 vsync video vertical sync input (schmitt trig- ger) 34 r red video analog dac output 28 g green video analog dac output 27 b blue video analog dac output 26 fb fast blanking analog dac output 25 ccvideo1 closed caption composite video input 1 (2v +/- 3 db) 15 fcpu cpu frequency multiplier filter output 31 fosd osd frequency multiplier filter output 33 test0 test input (must be tied to v dd )55
241/268 st92e196a/b & st92t196a/b general description pin description (contd) 1.2.1 i/o port configuration all ports can be individually configured as input, bi- directional, output, or alternate function. refer to the port bit configuration table in the i/o port chapter. no i/o pins have any physical weak pull-up capa- bility (they will show no pull-up if they are pro- grammed in the "weak pull-up" software mode). input levels can be selected on a bit basis by choosing between ttl or cmos input levels for i/ o port pin except for p2.(5:4,0), p3.(6:3,1:0), p4.(1:0) which are implemented with a schmitt trigger function. all port output configurations can be software se- lected on a bit basis to provide push-pull or open drain driving capabilities. for all ports, when con- figured as open-drain, the voltage on the pin must never exceed the v dd power line value (refer to electrical characteristics section). 1.2.2 i/o port reset state i/os are reset asynchronously as soon as the re- set pin is asserted low. all i/o are forced by the reset in bidirectional, high impedance output due to the lack of physical pull- up except p5.0 (refer to the reset section) which is forced into the "push-pull alternate function" mode until being reconfigured by software. warning when a common pin is declared to be connected to an alternate function input and to an alternate function output, the user must be aware of the fact that the alternate function output signal always in- puts to the alternate function module declared as input. when any given pin is declared to be connected to a digital alternate function input, the user must be aware of the fact that the alternate function input is always connected to the pin. when a given pin is declared to be connected to an analog alternate function input (adc input for example) and if this pin is programmed in the "af-od" mode, the digit- al input path is disconnected from the pin to pre- vent any dc consumption. table 48. i/o port characteristics legend: od = open drain, af = alternate function input output weak pull-up reset state port 0[7:0] ttl/cmos push-pull/od no bidirectional port 2.0 port 2[3:1] port 2[5:4] port 2[7:6] schmitt trigger ttl/cmos schmitt trigger ttl/cmos push-pull/od push-pull/od push-pull/od push-pull/od no no no no bidirectional bidirectional bidirectional bidirectional port 3.0 port 3.1 port 3.2 port 3[6:3] port 3.7 schmitt trigger schmitt trigger ttl/cmos schmitt trigger ttl/cmos push-pull/od push-pull/od push-pull/od push-pull/od push-pull/od no no no no no bidirectional bidirectional bidirectional bidirectional bidirectional port 4.[1:0] port 4.[7:2] schmitt trigger ttl/cmos push-pull/od push-pull/od no no bidirectional bidirectional port 5.0 port 5[6:1] ttl/cmos ttl/cmos push-pull/od push-pull/od no no push-pull af out bidirectional
242/268 st92e196a/b & st92t196a/b general description table 49. i/o port alternate functions port name general purpose i/o pin no. alternate functions sdip56 p0.0 all ports useable for general pur- pose i/o (input, output or bidi- rectional) 14 i/o p0.1 13 i/o p0.2 12 i/o p0.3 11 ain0 i a/d analog data input 0 p0.4 10 ain4 i a/d analog data input 4 p0.5 9 ain5 i a/d analog data input 5 p0.6 8 ain6 i a/d analog data input 6 p0.7 7 ain7 i a/d analog data input 7 p2.0 36 ir i ifr infrared input int7 i external interrupt 7 p2.1 37 ain1 i a/d analog data input 1 int6 i external interrupt 6 p2.2 38 int3 i external interrupt 3 ain2 a/d analog data input 2 vso1 o voltage synthesis converter output 1 p2.3 39 int4 i external interrupt 4 ain3 i a/d analog data input 3 vso2 o voltage synthesis converter output 2 p2.4 3 int2 i external interrupt 2 scl1 i/o i 2 c channel 1 serial clock sck o spi serial clock output p2.5 4 sdio i/o spi serial data sda1 i/o i 2 c channel 1 serial data p2.6 5 nmi i non maskable interrupt input p2.7 6 int5 i external interrupt 5 pixclk o pixel clock (after divide-by-2) output p3.0 24 scl3 i/o i 2 c channel 3 serial clock tslu o translucency digital video output p3.1 23 sda3 i/o i 2 c channel 3 serial data p3.2 22 int0 i external interrupt 0 p3.3 21 syndet1 i sync error detector input 1 dsout2 o data slicer comparator output 2 p3.4 20 int1 i external interrupt 1 scl2 i/o i 2 c channel 2 serial clock touta o mft timer output a p3.5 19 tina i mft timer input a sda2 i/o i 2 c channel 2 serial data
243/268 st92e196a/b & st92t196a/b general description p3.6 all ports useable for general pur- pose i/o (input, output or bidi- rectional) 18 syndet0 i sync error detector input 0 dsout1 o data slicer comparator output 1 p3.7 17 ccvideo2 i closed caption composite video input 1 (2v +/- 3 db) p4.0 43 scl4 i/o i 2 c channel 4 serial clock toutb o mft timer output b pwm0 o pwm d/a converter output 0 p4.1 44 tinb i mft timer input b sda4 i/o i 2 c channel 4 serial data pwm1 o pwm d/a converter output 1 p4.2 45 i/o p4.3 46 i/o p4.4 47 pwm4 o pwm d/a converter output 4 p4.5 48 pwm5 o pwm d/a converter output 5 p4.6 49 pwm6 o pwm d/a converter output 6 p4.7 50 extrg i a/d converter external trigger input pwm7 o pwm d/a converter output 7 p5.0 52 reseti o internal delayed reset output p5.1 53 sin0 i sci serial comm. interface input p5.2 54 sout0 o sci serial comm. interface output p5.5 1 pwm2 o pwm d/a converter output 2 p5.6 2 pwm3 o pwm d/a converter output 3 port name general purpose i/o pin no. alternate functions sdip56
244/268 st92e196a/b & st92t196a/b general description 1.3 required external components v pp test0 p5.2/sout0 p5.1/sin0 p.5.0/reseti reset p4.7/pwm7/extrg p4.6/pwm6 p4.5/pwm5 p4.4/pwm4 p4.3 p4.2 p4.1/sda4/tinb/pwm1 p4.0/scl4/toutb/pwm0 oscin v ss2 oscout p2.3/ain3/vso2/int4 p2.2/ain2/vso1/int3 p2.1/ain1/int6 p2.0/ir/int7 hsync vsync fosd v dda fcpu v ss1 v dd1 pwm2/p5.5 pwm3/p5.6 sck/scl1/int2/p2.4 sdio/sda1/p2.5 nmi/p2.6 pixclk/int5/p2.7 ain7/p0.7 ain6/p0.6 ain5/p0.5 ain4/p0.4 ain0/p0.3 p0.2 p0.1 p0.0 ccvideo1 v dd2 ccvideo2/p3.7 dsout1/syndet0/p3.6 tina/sda2/p3.5 int1/touta/scl2/p3.4 dsout2/syndet1/p3.3 int0/p3.2 sda3/p3.1 tslu/sdl3/p3.0 fb b g r 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 v dd (+5v) 270 10k 1mf sw-push v dd (+5v) gnd gnd gnd gnd 56pf 56pf 1m 4mhz osc. 1.2k 47nf gnd 1.2k 47nf 1f slicer 1 input 1f slicer 2 input (if present or used) + warning : the decoupling capacitors between analog and digital +5v (v dda , v dd1 , v dd2 ), and ground (v ss1 , v ss2 ) are not shown. add a 100nf and a 4.7f capacitor close to the corresponding pins if needed. 100pf 100pf
245/268 st92e196a/b & st92t196a/b general description 1.4 memory map figure 104. st92e196a/b & st92t196a/b memory map segment 20h 64 kbytes 200000h 21ffffh 20c000h 20bfffh 208000h 207fffh 204000h 203fffh page 80 - 16 kbytes page 81 - 16 kbytes page 82 - 16 kbytes page 83 - 16 kbytes reserved segment 21h 64 kbytes 20ffffh 220000h 22ffffh 210000h segment 22h 64 kbytes 220000h 22017fh 384 bytes osdram page 88 - 16 kbytes page 89 - 16 kbytes page 90 - 16 kbytes page 91 - 16 kbytes 22c000h 22bfffh 228000h 227fffh 224000h 223fffh 200000h 21ffffh 20c000h 20bfffh 208000h 207fffh 204000h 203fffh page 80 - 16 kbytes page 81 - 16 kbytes page 82 - 16 kbytes page 83 - 16 kbytes reserved 20ffffh 220000h 210000h page 88 - 16 kbytes page 89 - 16 kbytes page 90 - 16 kbytes page 91 - 16 kbytes 22c000h 22bfffh 228000h 227fffh 224000h 223fffh 200000h 21ffffh 20c000h 20bfffh 208000h 207fffh 204000h 203fffh page 80 - 16 kbytes page 81 - 16 kbytes page 82 - 16 kbytes page 83 - 16 kbytes reserved 20ffffh 220000h 22ffffh 210000h page 88 - 16 kbytes page 89 - 16 kbytes page 90 - 16 kbytes page 91 - 16 kbytes 22c000h 22bfffh 228000h 227fffh 224000h 223fffh 200000h 21ffffh 20c000h 20bfffh 208000h 207fffh 204000h 203fffh page 80 - 16 kbytes page 81 - 16 kbytes page 82 - 16 kbytes page 83 - 16 kbytes reserved 20ffffh 220000h 210000h page 88 - 16 kbytes page 89 - 16 kbytes page 90 - 16 kbytes page 91 - 16 kbytes 22c000h 22bfffh 228000h 227fffh 224000h 223fffh 20f000h internal ram 4 kbytes 20ffffh 010000h segment 0 64 kbytes 00ffffh 00c000h 00bfffh 008000h 007fffh 004000h 000000h 003fffh page 0 - 16 kbytes page 1 - 16 kbytes page 2 - 16 kbytes page 3 - 16 kbytes segment 1 64 kbytes 01ffffh 01c000h 01bfffh 018000h 017fffh 014000h 013fffh page 4 - 16 kbytes page 5 - 16 kbytes page 6 - 16 kbytes page 7 - 16 kbytes 010000h 00ffffh 00c000h 00bfffh 008000h 007fffh 004000h 000000h 003fffh page 0 - 16 kbytes page 1 - 16 kbytes page 2 - 16 kbytes page 3 - 16 kbytes 01ffffh 01c000h 01bfffh 018000h 017fffh 014000h 013fffh page 4 - 16 kbytes page 5 - 16 kbytes page 6 - 16 kbytes page 7 - 16 kbytes 128 kbytes 000000h 01ffffh eprom/otp 3 kbytes 20fbffh
246/268 st92e196a/b & st92t196a/b general description 1.5 st92e196a/b & st92t196a/b register map table 51 contains the map of the group f periph- eral pages. the common registers used by each peripheral are listed in table 50 . be very careful to correctly program both: C the set of registers dedicated to a particular function or peripheral. C registers common to other functions. C in particular, double-check that any registers with undefined reset values have been correct- ly initialised. warning : note that in the eivr and each ivr reg- ister, all bits are significant. take care when defin- ing base vector addresses that entries in the inter- rupt vector table do not overlap. table 50. common registers function or peripheral common registers sci, mft cicr + nicr + dma registers + i/o port registers adc cicr + nicr + i/o port registers wdt cicr + nicr + external interrupt registers + i/o port registers i/o ports i/o port registers + moder external interrupt interrupt registers + i/o port registers rccu interrupt registers + moder
247/268 st92e196a/b & st92t196a/b general description st92196a/b register map (contd) table 51. group f pages register map resources available on the st92e196a/b & st92t196a/b device: register page 0 2 3 9 101121244243444546555962 r255 res. res. res. res. mft res. mmu sci0 res. res. res. res. res. res. vs res. r254 spi port 3 tcc r253 res. r252 wcr osd res. pwm r251 wdt res. r250 port 2 ir/ sync err r249 r248 mft r247 ext int res. res. res. ds0 ds1 r246 port 5 rccu r245 res. i2c r244 r243 res. mft stim r242 port 0 port 4 adc r241 res. r240
248/268 st92e196a/b & st92t196a/b general description st92e196a/b/t196 register map (contd) table 52. detailed register map group f page dec. block reg. no. register name description reset value hex. doc. page n/a i/o port 0:5 r224 p0dr port 0 data register ff 69 r226 p2dr port 2 data register ff r227 p3dr port 3 data register ff r228 p4dr port 4 data register ff r229 p5dr port 5 data register ff core r230 cicr central interrupt control register 87 27 r231 flagr flag register 00 28 r232 rp0 pointer 0 register 00 30 r233 rp1 pointer 1 register 00 30 r234 ppr page pointer register 54 32 r235 moder mode register e0 32 r236 usphr user stack pointer high register xx 34 r237 usplr user stack pointer low register xx 34 r238 ssphr system stack pointer high reg. xx 34 r239 ssplr system stack pointer low reg. xx 34 0 int r242 eitr external interrupt trigger register 00 56 r243 eipr external interrupt pending reg. 00 56 r244 eimr external interrupt mask-bit reg. 00 56 r245 eiplr external interrupt priority level reg. ff 57 r246 eivr external interrupt vector register x6 57 r247 nicr nested interrupt control 00 57 wdt r248 wdthr watchdog timer high register ff 81 r249 wdtlr watchdog timer low register ff 81 r250 wdtpr watchdog timer prescaler reg. ff 81 r251 wdtcr watchdog timer control register 12 81 r252 wcr wait control register 7f 82 spi r253 spidr spi data register xx 190 r254 spicr spi control register 00 190 2 i/o port 0 r240 p0c0 port 0 configuration register 0 00 69 r241 p0c1 port 0 configuration register 1 00 r242 p0c2 port 0 configuration register 2 00 i/o port 2 r248 p2c0 port 2 configuration register 0 00 r249 p2c1 port 2 configuration register 1 00 r250 p2c2 port 2 configuration register 2 00 i/o port 3 r252 p3c0 port 3 configuration register 0 00 r253 p3c1 port 3 configuration register 1 00 r254 p3c2 port 3 configuration register 2 00
249/268 st92e196a/b & st92t196a/b general description 3 i/o port 4 r240 p4c0 port 4 configuration register 0 00 69 r241 p4c1 port 4 configuration register 1 00 r242 p4c2 port 4 configuration register 2 00 i/o port 5 r244 p5c0 port 5 configuration register 0 00 r245 p5c1 port 5 configuration register 1 00 r246 p5c2 port 5 configuration register 2 00 9 mft r240 dcpr dma counter pointer register xx 108 r241 dapr dma address pointer register xx 109 r242 t_ivr interrupt vector register xx 109 r243 idcr interrupt/dma control register c7 110 r248 iocr i/o connection register fc 110 10 r240 reg0hr capture load register 0 high xx 101 r241 reg0lr capture load register 0 low xx 101 r242 reg1hr capture load register 1 high xx 101 r243 reg1lr capture load register 1 low xx 101 r244 cmp0hr compare 0 register high 00 101 r245 cmp0lr compare 0 register low 00 101 r246 cmp1hr compare 1 register high 00 101 r247 cmp1lr compare 1 register low 00 101 r248 tcr timer control register 0x 102 r249 tmr timer mode register 00 103 r250 t_icr external input control register 0x 104 r251 prsr prescaler register 00 104 r252 oacr output a control register xx 105 r253 obcr output b control register xx 106 r254 t_flagr flags register 00 107 r255 idmr interrupt/dma mask register 00 108 11 stim r240 sth counter high byte register ff 86 r241 stl counter low byte register ff 86 r242 stp standard timer prescaler register ff 86 r243 stc standard timer control register 14 86 21 mmu r240 dpr0 data page register 0 00 39 r241 dpr1 data page register 1 01 39 r242 dpr2 data page register 2 02 39 r243 dpr3 data page register 3 83 39 r244 csr code segment register 00 40 r248 isr interrupt segment register x0 40 r249 dmasr dma segment register x0 40 extmi r246 emr2 external memory register 2 0f 58 group f page dec. block reg. no. register name description reset value hex. doc. page
250/268 st92e196a/b & st92t196a/b general description 24 sci0 r240 rdcpr receiver dma transaction counter pointer xx 201 r241 rdapr receiver dma source address pointer xx 201 r242 tdcpr transmitter dma transaction counter pointer xx 201 r243 tdapr transmitter dma destination address pointer xx 201 r244 s_ivr interrupt vector register xx 202 r245 acr address/data compare register xx 203 r246 imr interrupt mask register x0 203 r247 s_isr interrupt status register xx 204 r248 rxbr receive buffer register xx 205 r248 txbr transmitter buffer register xx 205 r249 idpr interrupt/dma priority register xx 206 r250 chcr character configuration register xx 207 r251 ccr clock configuration register 00 207 r252 brghr baud rate generator high reg. xx 208 r253 brglr baud rate generator low register xx 208 r254 sicr input control 03 208 r255 socr output control 01 208 42 osd r246 osdbcr2 border color register 2 x0 152 r247 osdbcr1 border color register 1 x0 152 r248 osder enable register 00 153 r249 osddr delay register xx 156 r250 osdfbr flag bit register xx 157 r251 osdslr scan line register xx 158 r252 osdmr mute register xx 158 43 ir/sync err r248 irpr infrared pulse register 00 169 r249 syncer sync error register 00 168 r250 irscr infrared / sync control register 00 168 tcc r253 mccr main clock control register 00 69 r254 skccr skew clock control register 00 69 44 i2c r240 i2coar own address register 00 175 r241 i2cfqr frequency register 00 176 r242 i2cctr control register 01 177 r243 i2cdr data register 00 178 r244 i2cstr2 status register 2 00 178 r245 i2cstr1 status register 1 00 179 group f page dec. block reg. no. register name description reset value hex. doc. page
251/268 st92e196a/b & st92t196a/b general description note: xx denotes a byte with an undefined value, however some of the bits may have defined values. refer to register description for details. 45 ds0 r240 ds0dr1 data register 1 00 164 r241 ds0dr2 data register 2 00 164 r242 ds0dr3 data register 3 00 164 r243 ds0dr4 data register 4 00 165 r244 ds0cr1 control register 1 00 165 r245 ds0cr2 control register 2 00 165 r246 ds0mr monitor register 00 166 46 ds1 r240 ds1dr1 data register 1 00 164 r241 ds1dr2 data register 2 00 164 r242 ds1dr3 data register 3 00 164 r243 ds1dr4 data register 4 00 165 r244 ds1cr1 control register 1 00 165 r245 ds1cr2 control register 2 00 165 r246 ds1mr monitor register 00 166 55 rccu r240 clkctl clock control register 00 64 r242 clk_flag clock flag register 48, 28 or 08 64 59 pwm r240 cm0 compare register 0 00 216 r241 cm1 compare register 1 00 216 r242 cm2 compare register 2 00 216 r243 cm3 compare register 3 00 216 r244 cm4 compare register 4 00 216 r245 cm5 compare register 5 00 216 r246 cm6 compare register 6 00 216 r247 cm7 compare register 7 00 216 r248 acr autoclear register ff 217 r249 ccr counter register 00 217 r250 pctl prescaler and control register 0c 217 r251 ocpl output complement register 00 218 r252 oer output enable register 00 218 vs r254 vsdr1 data and control register 1 00 213 r255 vsdr2 data register 2 00 213 62 adc r240 addtr channel i data register xx 221 r241 adclr control logic register 00 221 r242 adint ad interrupt register 01 222 group f page dec. block reg. no. register name description reset value hex. doc. page
252/268 st92e196a/b & st92t196a/b electrical characteristics 2 electrical characteristics the st92e196a/b & st92t196a/b devices con- tain circuitry to protect the inputs against damage due to high static voltage or electric field. never- theless, it is advised to take normal precautions and to avoid applying to this high impedance volt- age circuit any voltage higher than the maximum rated voltages. it is recommended for proper oper- ation that v in and v out be constrained to the range. v ss ( v in or v out ) v dd to enhance reliability of operation, it is recom- mended to connect unused inputs to an appropri- ate logic voltage level such as v ss or v dd . all the voltages in the following table, are refer- enced to v ss . absolute maximum ratings * current is limited to |<200 m a| into the pin note : stresses above those listed as absolute maximum ratings may cause permanent damage to the device. this is a stress rating o nly and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended p eriods may affect device reliability. recommended operating conditions note 1. 1mhz when a/d is used note 2. for good slicing results, it is advised to set vdda >= 5.3v. remember also that vdda < vdd + 0.3v. symbol parameter value unit v dd 1,2 supply voltage v ss C 0.3 to v ss + 7.0 v v dda analog supply voltage v ss C 0.3 to v dd +0.3 v v i input voltage v ss C 0.3 to v dd +0.3 v v i input voltage v ss C 0.7 to v dd +0.7 * v v o output voltage v ss C 0.3 to v dd +0.3 v v o output voltage v ss C 0.7 to v dd +0.7 * v t stg storage temperature C 55 to + 150 c i inj pin injection current digital and analog input -5 to +5 ma maximum accumulated pin injection current in the device -50 to +50 ma symbol parameter value unit min. max. t a operating temperature -10 75 c v dd operating supply voltage 4.5 5.5 v v dda analog supply voltage 4.5 5.5 v f osce external oscillator frequency 4.0 mhz f intclk internal clock frequency 0 1 24 mhz
253/268 st92e196a/b & st92t196a/b electrical characteristics dc electrical characteristics (v dd = 5v 10% t a = -10c + 75c, unless otherwise specified) note: all i/o ports are configured in bidirectional weak pull-up mode with no dc load external clock pin (oscin) is driven by square wave external clock. no peripheral working. symbol parameter test conditions value unit min. max. v ih input high level ttl 2.0 v cmos 0.7 v dd v v il input low level ttl 0.8 v cmos 0.3 v dd v v ihrs reset input high level 0.8 v dd v v ilrs reset input low level 0.3 v dd v v hyrs reset input hysteresis 0.5 v v ih p2.0 input high level 0.8 v dd v v il p2.0 input low level 0.3 v dd v v ihy p2.0 input hysteresis 0.5 v v ihiic sda4,1/scl4,1 input high level 0.8 v dd v v iliic sda4,1/scl4,1 input low level 0.3 v dd v v ihyiic sda4,1/scl4,1 hysteresis 0.5 v v ihvh hsync/vsync input high level 0.8 v dd v v ilvh hsync/vsync input low level 0.3 v dd v v hyhv hsync/vsync input hysteresis 1.2 v v ihdt syndet1,0 input high level 0.8 v dd v v ildt syndet1,0 input low level 0.3 v dd v v hydt syndet1,0 input hysteresis 0.5 v v oh output high level push pull, iload = C 0.8ma v dd C 0.8 v v ol output low level push pull or open drain, iload = 1.6ma 0.4 v v pp eprom programming voltage 12.8 v i lkio i/o pin input leakage current hi-z input, 0v < v in < v dd 1.0 m a i lkrs reset pin input leakage current 0v < v in < v dd 1.0 m a i lka/d a/d pin input leakage current alternate function open drain 1.0 m a i lkos oscin pin input leakage current 0v < v in < v dd 1.0 m a
254/268 st92e196a/b & st92t196a/b electrical characteristics ac electrical characteristics pin capacitance (v dd = 5v 10%; t a = -10c + 75c, unless otherwise specified) current consumption (v dd = 5v 10%; t a = -10c + 75c, unless otherwise specified) notes : 1. all ports are configured in push-pull output mode (output is high). vsync and hsync are tied to v ss , ccvideo is floating. the internal clock prescaler is in divide-by-1 mode. the external clock pin (oscin) is driven by a square wave external clock at 4 mhz. 2. the cpu is fed by a frequency issued by the on-chip frequency multiplier. the skew corrector frequency multiplier provides a 28 mhz clock. all peripherals are working. 3. all ports are configured in push-pull output mode (output is high). vsync and hsync are tied to v ss , ccvideo is floating. external clock pin (oscin) and reset pins are held low. all peripherals are disabled. 4. all ports are configured in push-pull output mode (output is high). vsync and hsync are tied to v ss , ccvideo is floating. all peripherals are disabled. 5. the cpu is fed by a frequency issued by the on-chip frequency multiplier. the skew corrector frequency multiplier provides a 14mhz clock. osd, a/d, pwm, sync error detector, std timer and wdg timer peripherals are running. symbol parameter conditions value unit typ. max c io pin capacitance digital input/output 810pf symbol parameter conditions value unit typ. max i cc1 run mode current (notes 1, 2) intclk=16mhz 80 100 ma i cc2 run mode current (notes 1, 2) intclk=24mhz 100 120 ma i cc3 run mode current (notes 1, 2) intclk=4mhz 25 30 ma i cc4 run mode current (notes 1, 5) intclk=16mhz 65 78 ma i cca1 analog current (v dda pin) freq. multipliers , a/d, osd, all dacs & slicers on. 45 55 ma i cca2 analog current (v dda pin) freq. multipliers , a/d, osd, dacs & slicers off. 110 a i cca3 analog current (v dda pin) freq. multipliers , a/d, osd, two dacs & one slicer on. 25 30 ma i ilpr reset mode current (note 3) 10 100 m a i halt halt mode current (note 4) 10 100 m a
255/268 st92e196a/b & st92t196a/b electrical characteristics ac electrical characteristics (contd) clock timing (v dd = 5v 10% t a = -10c + 75c, unless otherwise specified) external interrupt timing (rising or falling edge mode; v dd = 5v 10%; t a = -10c + 75c, unless otherwise specified) note: the value in the left hand two columns shows the formula used to calculate the minimum or maximum timing from the oscilla tor clock period, prescale value and number of wait cycles inserted. the value in the rignt hand two columns shows the minimum and maximu m for an external clock at 24 mhz divided by 2, prescale value of zero and zero wait status. external interrupt timing symbol parameter conditions value unit min max tpc oscin clock period intern. div. by 2 41.7 ns intern. div. by 1 83.3 ns trc oscin rise time 12 ns tfc oscin fall time 12 ns twcl oscin low width intern. div. by 2 17 ns intern. div. by 1 38 ns twch oscin high width intern. div. by 2 17 ns intern. div. by 1 38 ns n symbol parameter conditions unit oscin divided by 2 min. oscin not divided by 2 min. min max 1 twlr low level minimum pulse width in rising edge mode 2tpc + 12 tpc + 12 95 ns 2 twhr high level minimum pulse width in rising edge mode 2tpc + 12 tpc + 12 95 ns 3 twlf low level minimum pulse width in falling edge mode 2tpc + 12 tpc + 12 95 ns 4 twhf high level minimum pulse width in falling edge mode 2tpc + 12 tpc + 12 95 ns intn 1 23 4 rising edge detection falling edge detection n = 0-7 va00112
256/268 st92e196a/b & st92t196a/b electrical characteristics ac electrical characteristics (contd) spi timing (v dd = 5v 10% ; t a = -10c + 75c, unless otherwise specified) spi timing skew corrector timing table (v dd = 5v 10%; t a = -10c + 75c, unless otherwise specified) the osd jitter is measured from leading edge to leading edge of a single character row on consecutive tv lines. the value is an envelope of 100 fields *max. value at all cpu operating frequencies n symbol parameter conditions value unit min max 1 tsdi input data set-up time 100 2 thdi input data hold time 1/2 tpc + 100 3 tdov sck to output data valid 100 4 thdo output data hold time -20 5 twskl sck low pulse width 300 6 twskh sck high pulse width 300 sck sdo 5 6 sdi 1 2 4 3 va00109 symbol parameter conditions value max unit tjskw jitter on rgb output 28 mhz skew corrector clock frequency <12 * ns
257/268 st92e196a/b & st92t196a/b electrical characteristics ac electrical characteristics (contd) osd dac characteristics (v dd = 5v 10%; t a = -10c + 75c, unless otherwise specified) (*) output voltage matching of the r,g and b levels on a single device for each of the 8 levels (**) phase matching (50% point on both rise & fall time) on r, g, b, fb lines (fb in dac mode) (***) phase matching (50% point on both rise & fall time) on r, g, b, fb lines (fb in digital mode) (****) 95% of the signal amplitude is reached within the specified clock period symbol parameter conditions value unit min typ max output impedance fb,r,g,b 100 ohm output voltage fb,r,g,b cload = 20 pf rl=100k code = 111 code = 110 code = 101 code = 100 code = 011 code = 010 code = 001 code = 000 0.976 0.863 0.751 0.638 0.525 0.412 0.300 0.157 1.170 1.034 0.899 0.763 0.627 0.491 0.356 0.220 1.364 1.205 1.046 0.887 0.729 0.570 0.411 0.252 v fb = 1 fb = 0 5.0 0.2 v relative voltage accuracy (*) +/-5 % r/g/b to fb 50% point matching fb dac mode (**) 5ns r/g/b to fb 50% point matching fb digital mode (***) 5ns pixel frequency cload = 20 pf 20**** mhz. cload = 10 pf 40**** mhz.
258/268 st92e196a/b & st92t196a/b electrical characteristics ac electrical characteristics (contd) n/a = not applicable cb = capacitance of one bus in pf i 2 c interface electrical specifications symbol parameter standard mode i2c fast mode i2c unit min max min max v il low level input voltage: fixed input levels v dd -related input levels -0.5 -0.5 1.5 0.3 v dd -0.5 -0.5 1.5 0.3 v dd v v ih high level input voltage: v dd -related input levels 0.8 v dd v dd +0.5 0.8 v dd v dd +0.5 v v hys hysteresis of schmitt trigger inputs fixed input levels v dd -related input levels n/a n/a n/a n/a 0.2 0,05 v dd v t sp pulse width of spikes which must be sup- pressed by the input filter n/a n/a 0 ns 50 ns ns v ol1 v ol2 low level output voltage (open drain and open collector) at 3 ma sink current at 6 ma sink current 0 n/a 0.4 n/a 0 0 0.4 0.6 v t of output fall time from vih min to vil max with a bus capacitance from 10 pf to 400 pf with up to 3 ma sink current at v ol1 with up to 6 ma sink current at v ol2 n/a 250 n/a 20+0.1c b 20+0.1c b 250 250 ns i input current each i/o pin with an input voltage between 0.4v and 0.9 v dd max - 10 10 -10 10 m a c capacitance for each i/o pin 10 10 pf
259/268 st92e196a/b & st92t196a/b electrical characteristics ac electrical characteristics (contd) 1)the device must internally provide a hold time of at least 300 ns for the sda signal in order to bridge the unde- fined region of the falling edge of scl 2)the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal cb = total capacitance of one bus line in pf table 53. characteristics of analog input section (v dd = 5v, ta = -10c to 75c) measurement conditions: (*) same dc level on both comparator inputs ac level 40mv for applicated measurement sig- nal (**) corresponds to 25 ire tap voltage i 2 c bus timings symbol parameter standard i 2 c fast i 2 c unit min max min max t buf bus free time between a stop and start con- dition 4.7 1.3 m s t hd:sta hold time start condition. after this period, the first clock pulse is generated 4.0 0.6 m s t low low period of the scl clock 4.7 1.3 m s t high high period of the scl clock 4.0 0.6 m s t su:sta set-up time for a repeated start condition 4.7 0.6 m s t hd:dat data hold time 0 (1) 0 (1) 0.9(2) ns t su:dat data set-up time 250 100 ns t r rise time of both sda and scl signals 1000 20+0.1cb 300 ns tf fall time of both sda and scl signals 300 20+0.1cb 300 ns t su : sto set-up time for stop condition 4.0 0.6 ns cb capacitive load for each bus line 400 400 pf parameter value unit min. typ. max. voltage comparator reference voltage: unit#1 - video black level clamp 1.90 2.00 2.10 v unit#2 - data slicer (**) 2.25 2.35 2.45 v unit#3 - sync slicer 1.70 1.80 1.90 v voltage comparator delay (all units) (*) 150 200 250 ns video clamp: sink current (ccvideo pin at 2.1v dc) 21 42 80 a source current (ccvideo pin at 1.9v dc) 150 300 600 a sink to source current ratio 0.1 0.14 0.18
260/268 st92e196a/b & st92t196a/b electrical characteristics ac electrical characteristics (contd) a/d converter, external trigger timing table ( v dd = 5v +/-10%; t a = -10c to 75c, unless otherwise specified) a/d converter, external trigger timing table a/d converter. analog parameters table ( v dd = 5v +/-10% ; t a = -10c to 75c, unless otherwise specified)) notes: (*) the values are expected at 25 celsius degrees with v dd = 5v (**)'lsbs' , as used here, as a value of v dd /256 (1) @ 24 mhz external clock (2) including sample time (3) it must be considered as the on-chip series resistance before the sampling capacitor (4) dnl error= max {[v(i) -v(i-1)] / lsb-1}inl error= max {[v(i) -v(0)] / lsb-i} absolute accuracy= overall max conversion error n symbol parameter conditions value unit min max 1t low pulse width 1.5 intclk 2t high pulse distance 1.5 intclk 3t ext period/fast mode 78+1 intclk 4t str start conversion delay 0.5 1.5 intclk parameter value unit note typ (*) min max (**) analog input range v ss v dd v conversion time 138 intclk (1,2) sample time 87.51 intclk (1) power-up time 60 s resolution 8 bits differential non linearity 0.5 0.3 1.5 lsbs (4) integral non linearity 2 lsbs (4) absolute accuracy 2 lsbs (4) input resistance 1.5 kohm (3) hold capacitance 1.92 pf extrg 1 2 st (start conversion bit) 3 4 4 vr001401
261/268 st92e196a/b & st92t196a/b electrical characteristics ac electrical characteristics (contd) latch-up and esd ppm requirements parameter conditions value unit esd sensitivity for 10m a4 kv for 1m a2 latch-up performance stmicroelectronics specification for class a no latch-up parameter conditions value unit ppm requirements 100 ppm
262/268 st92e196a/b & st92t196a/b eprom/otp programming 3 eprom/otp programming the eprom/otp of the st92e196a/b & st92t196a/b devices may be programmed using the eprom programming boards available from stmicroelectronics. eprom erasing the eprom of the windowed package of the st92e196a/b can be erased by exposure to ul- tra-violet light. the erasure characteristic of the st92e196a/b is such that erasure begins when the memory is ex- posed to light with wave lengths shorter than ap- proximately 4000?. it should be noted that sunlight and some types of fluorescent lamps have wave- lengths in the range 3000-4000 ?. it is recom- mended to cover the window of the st92e196a/b packages by an opaque label to prevent uninten- tional erasure problems when testing the applica- tion in such an environment. the recommended erasure procedure of the eprom is the exposure to short wave ultraviolet light which have a wave-length 2537?. the inte- grated dose (i.e. u.v. intensity x exposure time) for erasure should be a minimum of 15w-sec/cm2. the erasure time with this dosage is approximate- ly 30 minutes using an ultraviolet lamp with a 12000 mw/cm2 power rating. the device should be placed within 2.5 cm (1 inch) of the lamp tubes during erasure.
263/268 st92e196a/b & st92t196a/b package description 4 package description figure 105. 56-pin shrink ceramic dual in-line package, 600-mil width figure 106. 56-pin shrink plastic dual in line package, 600-mil width dim. mm inches min typ max min typ max a 4.17 0.164 a1 0.76 0.030 b 0.38 0.46 0.56 0.015 0.018 0.022 b1 0.76 0.89 1.02 0.030 0.035 0.040 c 0.23 0.25 0.38 0.009 0.010 0.015 d 50.04 50.80 51.56 1.970 2.000 2.030 d1 48.01 1.890 e1 14.48 14.99 15.49 0.570 0.590 0.610 e 1.78 0.070 g 14.12 14.38 14.63 0.556 0.566 0.576 g1 18.69 18.95 19.20 0.736 0.746 0.756 g2 1.14 0.045 g3 11.05 11.30 11.56 0.435 0.445 0.455 g4 15.11 15.37 15.62 0.595 0.605 0.615 l 2.92 5.08 0.115 0.200 s 1.40 0.055 number of pins n56 cdip56sw dim. mm inches min typ max min typ max a 6.35 0.250 a1 0.38 0.015 a2 3.18 4.95 0.125 0.195 b 0.41 0.016 b2 0.89 0.035 c 0.20 0.38 0.008 0.015 d 50.29 53.21 1.980 2.095 e 15.01 0.591 e1 12.32 14.73 0.485 0.580 e 1.78 0.070 ea 15.24 0.600 eb 17.78 0.700 l 2.92 5.08 0.115 0.200 number of pins n56 psdip56
264/268 st92e196a/b & st92t196a/b ordering information 5 ordering information device memory (kbytes) ram (kbytes) data slicers sci mft package st92e196a9 128 (eprom) 4211 csdip56w st92t196a9 128 (otp) psdip56 st92e196b7 128 (eprom) 3211 csdip56w st92t196b7 128 (otp) psdip56
265/268 st92e196a/b & st92t196a/b ordering information st9e2196a/b & st92t196a/b option list customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no: . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference/rom code* : . . . . . . . . . . . . . . . . . . *the rom code name is assigned by stmicroelectronics. please confirm characteristics of device: device: [ ] st92e196a9 [ ] st92t196a9 128k eprom 128k otp [ ] st92e196b7 [ ] st92t196b7 128k eprom 128k otp package: [ ] csdip56w [ ] psdip56 temperature range: -10c to 75 c osd code (a version only):[ ] osd filename _ _ _ _ _ _ _ _ _.osd special marking: [ ] no [ ] yes "_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _" for marking, one line is possible with maximum 14 characters. authorized characters are letters, digits, '.', '-', '/' and spaces only. quantity forecast: [ _ _ _ _ _ _ _] k units per year for a period of [ _ _ ] years. preferred production start date: [ _ _ _ _ _ _ _] (yyyy/mm/dd) date . . . . . . . . . . . . . . . . . . . . . . . . . . . . customer signature . . . . . . . . . . . . . . . . . . . . .
266/268 st92e196a/b & st92t196a/b summary of changes 12 summary of changes 3.0 addition of st92t196b and st92e196b salestypes. i2c bus interface speed changed from up to 800 khz to 666.67 khz. qfp64 package removed. 31 aug 2001 3.1 vdda recommendation for good slicing results added. 27 feb 2003
267/268 st92e196a/b & st92t196a/b summary of changes
268/268 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroele ctronics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - sin gapore - spain sweden - switzerland - united kingdom - u.s.a. http://www.st.com 4

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